公开(公告)号：US10978510B2

公开(公告)日：2021-04-13

申请号：US16443255

申请日：2019-06-17

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Pinghui Li ,  Haiqing Zhou ,  Liying Zhang ,  Wanbing Yi ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Darin Chan

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  G11C11/16 ,  H01L27/02 ,  H01L43/12 ,  G11C11/15

摘要： Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

公开(公告)号：US10381360B1

公开(公告)日：2019-08-13

申请号：US15933069

申请日：2018-03-22

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Laiqiang Luo ,  Sen Mei ,  Fangxin Deng ,  Zhiqiang Teo ,  Fan Zhang ,  Pinghui Li ,  Haiqing Zhou ,  Xingyu Chen ,  Kin Leong Pey

IPC分类号： H01L27/115 ,  H01L27/11546 ,  H01L27/11521 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/265 ,  H01L29/423

摘要： A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

公开(公告)号：US10374005B2

公开(公告)日：2019-08-06

申请号：US15858655

申请日：2017-12-29

申请人： GLOBALFOUNDRIES Singapore Pte. ltd.

发明人： Pinghui Li ,  Haiqing Zhou ,  Liying Zhang ,  Wanbing Yi ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Darin Chan

IPC分类号： G11C5/02 ,  H01L27/02 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.