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公开(公告)号:US09520506B2
公开(公告)日:2016-12-13
申请号:US14338354
申请日:2014-07-23
发明人: Laiqiang Luo , Xinshu Cai , Danny Shum , Fan Zhang , Khee Yong Lim , Juan Boon Tan , Shaoqiang Zhang
IPC分类号: H01L29/94 , H01L29/66 , H01L23/522 , H01L27/08 , H01L49/02
CPC分类号: H01L29/94 , H01L23/5223 , H01L27/0805 , H01L28/86 , H01L28/90 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics. The C3 includes a first C3 plate served by the gate electrode, a second C3 plate served by second group lines in the first metal level of the ILD layers, and a C3 capacitor dielectric is served by the first via level dielectric below M1 and above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C1, C2 and C3 and a second capacitor terminal is coupled to second capacitor plates of C1, C2 and C3.
摘要翻译: 提出了一种形成电容器的电容器和方法。 电容器包括具有其中设置电容器的电容器区域的基板。 电容器包括第一,第二和第三子电容器(C1,C2和C3)。 C1包括在衬底上包括栅极的金属氧化物半导体(MOS)电容器。 栅极包括位于栅极电介质上的栅电极。 第一C1板由栅极电极供电,第二C1板由电容器区域的衬底供电,C1电容器电介质由栅极电介质供电。 C2包括设置在具有金属电平和通孔电平的ILD层中的后端行(BEOL)垂直电容器。 多个金属线设置在金属层中。 金属层的金属线以交替的第一和第二组分组,第一组用作第一C2板,第二组用作第二C2板,并且第一和第二组之间的介电层用作C2电容器电介质。 C3包括由栅电极服务的第一C3板,由ILD层的第一金属层中的第二组线服务的第二C3板,并且C3电容器电介质由位于M1之下的第一通孔级电介质和 栅电极。 第一电容器端子耦合到C1,C2和C3的第一电容器板,并且第二电容器端子耦合到C1,C2和C3的第二电容器板。
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2.
公开(公告)号:US09929165B1
公开(公告)日:2018-03-27
申请号:US15278112
申请日:2016-09-28
发明人: Laiqiang Luo , Yu Jin Eugene Kong , Daxiang Wang , Fan Zhang , Danny Pak-Chum Shum , Pinghui Li , Zhiqiang Teo , Juan Boon Tan , Soh Yun Siah , Pey Kin Leong
IPC分类号: H01L27/07 , H01L27/11521 , H01L21/027 , H01L29/66 , H01L29/06 , H01L21/768 , H01L21/308 , H01L21/3205 , H01L21/265
CPC分类号: H01L27/11521 , H01L21/0273 , H01L21/26513 , H01L21/28273 , H01L21/3081 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L29/0649 , H01L29/66825
摘要: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.
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公开(公告)号:US10381360B1
公开(公告)日:2019-08-13
申请号:US15933069
申请日:2018-03-22
发明人: Laiqiang Luo , Sen Mei , Fangxin Deng , Zhiqiang Teo , Fan Zhang , Pinghui Li , Haiqing Zhou , Xingyu Chen , Kin Leong Pey
IPC分类号: H01L27/115 , H01L27/11546 , H01L27/11521 , H01L21/02 , H01L21/321 , H01L21/3213 , H01L21/265 , H01L29/423
摘要: A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.
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4.
公开(公告)号:US20180090505A1
公开(公告)日:2018-03-29
申请号:US15278112
申请日:2016-09-28
发明人: Laiqiang Luo , Yu Jin Eugene Kong , Daxiang Wang , Fan Zhang , Danny Pak-Chum Shum , Pinghui Li , Zhiqiang Teo , Juan Boon Tan , Soh Yun Siah , Pey Kin Leong
IPC分类号: H01L27/115 , H01L21/027 , H01L29/66 , H01L29/06 , H01L21/768 , H01L21/308 , H01L21/3205 , H01L21/265
CPC分类号: H01L27/11521 , H01L21/0273 , H01L21/26513 , H01L21/28273 , H01L21/3081 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L29/0649 , H01L29/66825
摘要: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.
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公开(公告)号:US09679905B1
公开(公告)日:2017-06-13
申请号:US15094555
申请日:2016-04-08
发明人: Laiqiang Luo , Yew Tuck Clament Chow , Fan Zhang , Huajun Liu , Dong Wang , Danny Pak-Chum Shum , Juan Boon Tan
IPC分类号: H01L21/28 , H01L27/11 , H01L27/11556 , H01L27/11582 , H01L29/423 , H01L21/66 , H01L27/1157 , H01L27/11524 , H01L27/11529 , H01L27/11573 , H01L27/11565 , H01L27/11519 , H01L21/3213 , H01L21/285
CPC分类号: H01L21/28556 , H01L21/28273 , H01L21/28525 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L22/26 , H01L27/11534 , H01L27/11573 , H01L29/42328
摘要: Integrated circuits and methods of producing the same are provide. In an exemplary embodiment, a method includes determining a memory area of the integrated circuit, and forming a select layer overlying the substrate. A portion of the select layer is selectively etched to form a select gate within the memory area. A concentration of an indicator is measured in an etch off-gas during the selective etching of the select layer, and the selective etching of the select layer is terminated when the concentration of the indicator crosses an end point determination concentration.
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