公开(公告)号：US11145348B1

公开(公告)日：2021-10-12

申请号：US16871129

申请日：2020-05-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Steven R. Soss

IPC: G11C14/00 ,  G11C11/16 ,  G11C7/10

Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.

公开(公告)号：US11101348B2

公开(公告)日：2021-08-24

申请号：US16044544

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Julien Frougier ,  Nigel G. Cave ,  Steven R. Soss ,  Daniel Chanemougame ,  Steven Bentley ,  Rohit Galatage ,  Bum Ki Moon

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/768 ,  H01L27/088 ,  B82Y40/00 ,  B82Y30/00

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

公开(公告)号：US20210142850A1

公开(公告)日：2021-05-13

申请号：US16677790

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Steven R. Soss ,  Bipul C. Paul

IPC: G11C13/00 ,  H01L27/24

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

公开(公告)号：US11004509B1

公开(公告)日：2021-05-11

申请号：US16677790

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven R. Soss ,  Bipul C. Paul

IPC: G11C13/00 ,  H01L27/24

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

公开(公告)号：US11475941B2

公开(公告)日：2022-10-18

申请号：US17110674

申请日：2020-12-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. Jaiswal ,  Bipul C. Paul ,  Steven R. Soss

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

公开(公告)号：US20220068340A1

公开(公告)日：2022-03-03

申请号：US17007512

申请日：2020-08-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Steven R. Soss

IPC: G11C11/16 ,  G11C7/20 ,  G11C5/06

Abstract: Disclosed are embodiments of a non-volatile static random access memory (NV-SRAM) cell. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. These NVM circuits capture data values stored on the data nodes of the SRAM circuit prior to power down and rewrite those data values back onto the data nodes of the SRAM circuit upon power up. Also disclosed are embodiments of a method of operating a selected NV-SRAM cell in a memory array.