公开(公告)号：US20120311269A1

公开(公告)日：2012-12-06

申请号：US13153102

申请日：2011-06-03

申请人： Gabriel H. Loh ,  Jaewoong Chung ,  Nuwan Jayasena ,  Steve Reinhardt ,  James O'Connor ,  Kevin McGrath

发明人： Gabriel H. Loh ,  Jaewoong Chung ,  Nuwan Jayasena ,  Steve Reinhardt ,  James O'Connor ,  Kevin McGrath

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  Y02D10/13

摘要： An apparatus is disclosed for caching memory data in a computer system with multiple system memories. The apparatus comprises a data cache for caching memory data. The apparatus is configured to determine a retention priority for a cache block stored in the data cache. The retention priority is based on a performance characteristic of a system memory from which the cache block is cached.

摘要翻译： 公开了一种用于在具有多个系统存储器的计算机系统中缓存存储器数据的装置。 该装置包括用于缓存存储器数据的数据高速缓存。 该装置被配置为确定存储在数据高速缓存中的高速缓存块的保留优先级。 保留优先级基于高速缓存块被缓存的系统存储器的性能特性。

公开(公告)号：US08621131B2

公开(公告)日：2013-12-31

申请号：US13221465

申请日：2011-08-30

申请人： Gabriel H. Loh ,  Bradford M. Beckmann ,  Jaewoong Chung ,  Subho Chatterjee

发明人： Gabriel H. Loh ,  Bradford M. Beckmann ,  Jaewoong Chung ,  Subho Chatterjee

IPC分类号： G06F13/00

CPC分类号： G06F13/4265 ,  G06F2213/0038

摘要： Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.

摘要翻译： 公开了各种方法，计算机可读介质，制品和系统。 一方面，提供一种包括用第一半导体芯片产生分组的方法。 分组旨在传送第一衬底并由第二半导体芯片的节点接收。 分组包括分组报头和分组主体。 分组报头包括来自第一基板的第一出口点的标识和节点的标识。 分组被发送到第一衬底并且最终传送到第二半导体芯片的节点。

公开(公告)号：US20130054849A1

公开(公告)日：2013-02-28

申请号：US13221465

申请日：2011-08-30

申请人： Gabriel H. Loh ,  Bradford M. Beckmann ,  Jaewoong Chung ,  Subho Chatterjee

发明人： Gabriel H. Loh ,  Bradford M. Beckmann ,  Jaewoong Chung ,  Subho Chatterjee

IPC分类号： G06F13/00

CPC分类号： G06F13/4265 ,  G06F2213/0038

摘要： Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.

摘要翻译： 公开了各种方法，计算机可读介质，制品和系统。 一方面，提供一种包括用第一半导体芯片产生分组的方法。 分组旨在传送第一衬底并由第二半导体芯片的节点接收。 分组包括分组报头和分组主体。 分组报头包括来自第一基板的第一出口点的标识和节点的标识。 分组被发送到第一衬底并且最终传送到第二半导体芯片的节点。

公开(公告)号：US09880848B2

公开(公告)日：2018-01-30

申请号：US12814025

申请日：2010-06-11

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/467

摘要： A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

公开(公告)号：US09292221B2

公开(公告)日：2016-03-22

申请号：US13995943

申请日：2011-09-29

申请人： Cheng Wang ,  Youfeng Wu ,  Jaewoong Chung

发明人： Cheng Wang ,  Youfeng Wu ,  Jaewoong Chung

IPC分类号： G06F3/06 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F3/065 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

摘要： Embodiments of the present disclosure describe a processor, which may include copy circuitry coupled to a shadow register file and a control register. The copy circuitry may be configured to copy content from a range of a number of registers to a shadow range of the shadow register file in a forward or backward direction. The forward or backward direction may be based at least in part on a value stored in the control register.

摘要翻译： 本公开的实施例描述了一种处理器，其可以包括耦合到影子寄存器文件和控制寄存器的复制电路。 复制电路可以被配置为将内容从多个寄存器的范围向前或向后复制到影子寄存器文件的阴影范围。 前进或后退方向可以至少部分地基于存储在控制寄存器中的值。

公开(公告)号：US09032156B2

公开(公告)日：2015-05-12

申请号：US13177092

申请日：2011-07-06

申请人： Jaewoong Chung ,  Shekhar Srikantaiah ,  Lisa Hsu

发明人： Jaewoong Chung ,  Shekhar Srikantaiah ,  Lisa Hsu

IPC分类号： G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0842 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/62

摘要： For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

摘要翻译： 对于在数据处理设备的共享高速缓存处接收到的每个访问请求，如果请求的线程是唯一的线程，则存储器访问模式（MAP）监视器预测访问请求将访问哪个存储体和对应的行缓冲器 在数据处理装置执行。 通过针对多个访问请求记录对时间的预测访问，MAP监视器通过执行线程来开发预测的存储器访问的模式。 可以使用该模式来在共享高速缓存上分配资源，从而更有效地管理存储器。

公开(公告)号：US08854387B2

公开(公告)日：2014-10-07

申请号：US12975806

申请日：2010-12-22

申请人： Jaewoong Chung

发明人： Jaewoong Chung

IPC分类号： G09G5/39 ,  G06F13/00 ,  G09G5/00

CPC分类号： G09G5/001 ,  G09G5/39

摘要： A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.

摘要翻译： 公开了一种用于管理在系统存储器控制器和图形存储器控制器之间协调的存储器请求的系统和方法。 存储器请求根据源存储器控制器的优化策略进行预先安排，然后通过CPU / GPU边界将一批预先调度的请求发送到目标存储器控制器。 目标存储器控制器然后处理包含在预调度请求中的预调节决定，并且进而发送存储器请求作为源存储器控制器的代理。 因此，目标存储器控制器不需要执行CPU请求和GPU请求。

公开(公告)号：US20140122845A1

公开(公告)日：2014-05-01

申请号：US13993364

申请日：2011-12-30

申请人： Jaewoong Chung ,  Cheng Wang ,  Youfeng Wu

发明人： Jaewoong Chung ,  Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/467 ,  G06F9/528

摘要： In one embodiment, the present invention includes a processor having a core to execute instructions. This core can include various structures and logic that enable instructions of different atomic regions to be executed in an overlapping manner. To this end, the core can include a register file having registers to store data for use in execution of the instructions, and multiple shadow register files each to store a register checkpoint on initiation of a given atomic region. In this way, overlapping execution of atomic regions identified by a programmer or compiler can occur. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有执行指令的核心的处理器。 该核心可以包括能够以重叠的方式执行不同原子区域的指令的各种结构和逻辑。 为此，核心可以包括具有用于存储用于执行指令的数据的寄存器的寄存器文件，以及每个在给定原子区域的启动时存储寄存器检查点的多个影子寄存器文件。 以这种方式，可以发生由程序员或编译器识别的原子区域的重叠执行。 描述和要求保护其他实施例。

公开(公告)号：US08453150B2

公开(公告)日：2013-05-28

申请号：US12795871

申请日：2010-06-08

申请人： Jaewoong Chung

发明人： Jaewoong Chung

IPC分类号： G06F9/50 ,  G06F13/00

CPC分类号： G06F13/1605 ,  G06F9/5016

摘要： A device may include a memory controller that identifies a multithread application, and adjusts a memory scheduling scheme for the multithread application based on the identification of the multithread application.

摘要翻译： 设备可以包括识别多线程应用的存储器控​​制器，并且基于多线程应用的标识来调整多线程应用的存储器调度方案。

公开(公告)号：US08356130B2

公开(公告)日：2013-01-15

申请号：US12633032

申请日：2009-12-08

申请人： Karin Strauss ,  Jaewoong Chung

发明人： Karin Strauss ,  Jaewoong Chung

IPC分类号： G06F13/24

CPC分类号： G06F13/26 ,  G06F9/4818 ,  G06F13/4022

摘要： A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.

摘要翻译： 一种方法包括至少部分地基于包含在与用户级别中断相关联的用户级中断消息中的中断域标识符和中断接收者标识符，在邮箱中记录无法投递的用户级中断。 该记录至少部分地基于在多核系统中的多个处理器核的处理器核上执行的接收应用程序线程的用户级别中断不可投递的指示。