公开(公告)号：US20130130448A1

公开(公告)日：2013-05-23

申请号：US13502788

申请日：2012-02-28

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L29/511 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.

摘要翻译： 本发明提供了一种用于形成和控制分子水平SiO 2界面层的方法，主要包括：在生长SiO 2界面层之前进行清洗，生长分子级超薄SiO 2界面层; 并控制高K栅极电介质和SiO 2界面层之间的反应，以进一步降低SiO 2界面层。 本公开可以严格地防止过程整合期间的氧侵入。 本公开可以获得具有小EOT的优质高K电介质膜。 制造过程简单易于集成。 它还兼容平面CMOS工艺，可以满足45纳米以下节点的高性能纳米级CMOS金属栅极/高K器件的要求。

公开(公告)号：US20130005097A1

公开(公告)日：2013-01-03

申请号：US13379169

申请日：2011-08-02

申请人： Gaobo Xu ,  Qiuxia Xu

发明人： Gaobo Xu ,  Qiuxia Xu

IPC分类号： H01L21/8238 ,  H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/66545 ,  H01L21/823842

摘要： A method for integrating a replacement gate in a semiconductor device is disclosed. The method may comprise: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO2 layer on the semiconductor substrate; forming a SOG layer on the SiO2 layer; etching the SOG layer until the SiO2 layer is exposed; etching the SOG layer and the SiO2 layer at different rates in such a manner that the SiO2 layer is planarized; and forming a N-type replacement gate stack on the N-type device region and/or a P-type replacement gate stack on the P-type device region, respectively.

摘要翻译： 公开了一种在半导体器件中集成置换栅极的方法。 该方法可以包括：在半导体衬底上形成阱区，并且限定N型器件区和/或P型器件区; 在N型器件区域和/或P型器件区域上分别形成牺牲栅极堆叠或牺牲栅极堆叠，牺牲栅极堆叠或每个牺牲栅极堆叠包括牺牲栅极电介质层和牺牲栅极电极层 其中所述牺牲栅极电介质层设置在所述半导体衬底上，并且所述牺牲栅极电极层设置在所述牺牲栅极电介质层上; 形成围绕所述牺牲栅极叠层或相应的牺牲栅极叠层的间隔物或间隔物; 在牺牲栅极堆叠或相应的牺牲栅极堆叠的两侧上形成源极/漏极区域并嵌入到半导体衬底中; 在所述半导体衬底上形成SiO 2层; 在SiO 2层上形成SOG层; 蚀刻SOG层直到暴露SiO 2层; 以使SiO 2层平坦化的方式以不同的速率蚀刻SOG层和SiO 2层; 以及分别在P型器件区域上的N型器件区域和/或P型替换栅极堆叠上形成N型替换栅极堆叠。

公开(公告)号：US20110256701A1

公开(公告)日：2011-10-20

申请号：US12990735

申请日：2010-06-28

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/32136 ,  H01L21/3215 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO2 by high-temperature annealing so that the doped metal ions accumulate at the interface or generate dipoles by interfacial reaction, which in turn tunes the work function of the metal gate. The inventive method can be widely used and its process is simple and convenient, has a better ability of tuning the work function of the metal gate, and is compatible with the conventional CMOS process.

摘要翻译： 本申请公开了一种用于调谐PMOS器件的金属栅极的功函数的方法，包括以下步骤：通过物理气相沉积（PVD）将金属氮化物或金属层沉积在高k栅极电介质层上， 作为金属门; 通过离子注入对诸如Al，Pt，Ru，Ga，Ir的掺杂剂掺杂金属栅; 并通过高温退火将掺杂的金属离子驱动到高k栅极电介质和界面SiO 2之间的界面，使得掺杂的金属离子在界面处积累或通过界面反应产生偶极子，这进而调节了 金属门。 本发明的方法可以广泛使用，其工艺简单方便，具有更好的调谐金属栅极功能的能力，并且与传统的CMOS工艺兼容。

公开(公告)号：US08748250B2

公开(公告)日：2014-06-10

申请号：US13129743

申请日：2011-02-21

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated.

摘要翻译： 本发明提供了一种用于将双金属栅极和双栅极电介质集成到CMOS器件中的方法，包括：通过快速热氧化生长超薄界面氧化物层或氧氮化物层; 通过物理气相沉积在超薄界面氧化物层上形成高k栅介质层; 在沉积高k后进行快速热退火; 通过物理气相沉积沉积金属氮化物栅极; 通过用于PMOS器件的P型掺杂剂和用于NMOS器件的N型掺杂剂通过离子注入来掺杂金属氮化物栅极，其中光致抗蚀剂层作为掩模; 通过低压CVD工艺沉积多晶硅层和硬掩模，然后进行光刻工艺并蚀刻硬掩模; 去除光致抗蚀剂，然后依次蚀刻多晶硅层/金属栅极/高k电介质层以提供金属栅极叠层; 形成第一间隔物，并以低能量和大角度对源/漏延伸进行离子注入; 形成第二间隔物，并对源/漏区进行离子注入; 在源极/漏极区域中的掺杂剂被激活的过程中，分别进行热退火以调整用于NMOS和PMOS器件的金属栅极功函数。

公开(公告)号：US20140154853A1

公开(公告)日：2014-06-05

申请号：US13878046

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

发明人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

IPC分类号： H01L29/66

CPC分类号： H01L21/28176 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

摘要翻译： 本公开公开了一种用于制造N型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源极/漏极区，源/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US20130078773A1

公开(公告)日：2013-03-28

申请号：US13576658

申请日：2011-11-22

申请人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

发明人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

公开(公告)号：US20120115087A1

公开(公告)日：2012-05-10

申请号：US13123070

申请日：2011-02-15

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： G03F7/20

CPC分类号： G03F7/0035 ,  G03F7/2039 ,  G03F7/405

摘要： A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments.

摘要翻译： 提供了一种提高电子束曝光效率的方法，包括：步骤1）在正在加工的晶片上涂覆正性光致抗蚀剂，并进行预烘烤; 步骤2）分离图案数据，光学地暴露一组相对大的图案，然后进行后烘烤; 步骤3）显影正性光致抗蚀剂; 步骤4）进行等离子体氟化; 步骤5）进行烘烤以固化光致抗蚀剂; 步骤6）涂覆负电子束抗蚀剂并进行预烘烤; 步骤7）电子束暴露一组精细图案; 步骤8）进行后烘烤; 和步骤9）显影负电子束抗蚀剂，使得图案的制​​造完成。 根据本发明，可以节省30-60％的曝光时间。 因此，曝光效率显着提高，成本大大降低。 此外，该方法与CMOS工艺完全兼容，无需任何特殊设备。

公开(公告)号：US09049061B2

公开(公告)日：2015-06-02

申请号：US13640733

申请日：2012-04-11

申请人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

发明人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC分类号： H01L27/092 ,  H01L21/265 ,  H04L21/02

CPC分类号： H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

摘要： This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

摘要翻译： 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

公开(公告)号：US08822292B2

公开(公告)日：2014-09-02

申请号：US13502788

申请日：2012-02-28

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/336 ,  H01L29/51

CPC分类号： H01L29/511 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.

摘要翻译： 本发明提供了一种用于形成和控制分子水平SiO 2界面层的方法，主要包括：在生长SiO 2界面层之前进行清洗，生长分子级超薄SiO 2界面层; 并控制高K栅极电介质和SiO 2界面层之间的反应，以进一步降低SiO 2界面层。 本公开可以严格地防止过程整合期间的氧侵入。 本公开可以获得具有小EOT的优质高K电介质膜。 制造过程简单易于集成。 它还兼容平面CMOS工艺，可以满足45纳米以下节点的高性能纳米级CMOS金属栅极/高K器件的要求。

公开(公告)号：US20130099328A1

公开(公告)日：2013-04-25

申请号：US13125710

申请日：2011-02-27

申请人： Gaobo Xu ,  Qiuxia Xu

发明人： Gaobo Xu ,  Qiuxia Xu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

摘要翻译： 本申请提供了一种p型半导体器件及其制造方法。 该器件的结构包括：半导体衬底; 位于半导体衬底中的沟道区; 栅极堆叠，其位于包括栅极介电层和栅电极的沟道区上，其中所述栅极介电层位于所述沟道区上，并且所述栅电极位于所述栅极电介质层上; 以及源极/漏极区域，位于沟道区域的两侧并嵌入到半导体衬底中; 其中元件Al分布在栅极电介质层的上表面，底表面和栅电极的底表面中的至少一个中。 本发明的实施例可用于制造MOSFET。