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1.发明申请System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation 审中-公开双速定时脉冲发生系统和方法，具有消除干扰公开(公告)号：US20100266081A1
公开(公告)日：2010-10-21
申请号：US12427218
申请日：2009-04-21
IPC分类号： H04L7/00
CPC分类号： G06F1/10
摘要： A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer.
摘要翻译： 一种用于产生双速率时钟电路的方法，该方法包括通过至少一个反相器电路将第一本地时钟缓冲器的输出端耦合到第二本地时钟缓冲器的输入，并用基本信号驱动第一本地时钟缓冲器。 该方法还包括基于基本信号产生具有第一本地时钟缓冲器的早期时钟信号，并通过用至少一个反相器延迟第一本地时钟信号来产生延迟的早期时钟信号。 该方法还包括通过用延迟的早期时钟信号驱动第二本地时钟缓冲器来产生较后的时钟信号，其中由第二本地时钟缓冲器产生的第二本地时钟缓冲器和后期时钟信号同步并与第一本地时钟缓冲器相关联 和由第一本地时钟缓冲器产生的早期时钟信号。
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2.发明授权Implementing instruction set architectures with non-contiguous register file specifiers 有权用不连续的寄存器文件说明符来实现指令集体系结构公开(公告)号：US07793081B2
公开(公告)日：2010-09-07
申请号：US12062131
申请日：2008-04-03
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译： 提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。 一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。 固定宽度指令包括不连续的寄存器说明符。
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公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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4.发明授权公开(公告)号：US07349288B1
公开(公告)日：2008-03-25
申请号：US11538877
申请日：2006-10-05
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译： 超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址位转换为N个逻辑真地址位和N个互补地址位。 部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。 这些位组被划分以优化地址解码器中的并行位线的布局。
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5.发明授权公开(公告)号：US06667555B2
公开(公告)日：2003-12-23
申请号：US10301196
申请日：2002-11-21
IPC分类号： H01L2348
CPC分类号： H05K1/144 , H01L25/105 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.
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公开(公告)号：US08605489B2
公开(公告)日：2013-12-10
申请号：US13307884
申请日：2011-11-30
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译： 存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路 。 存储器件还包括与位和字线电路耦合的至少一个控制电路。 控制电路用于使状态信息存储在存储单元中。 至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。 控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。
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公开(公告)号：US08020073B2
公开(公告)日：2011-09-13
申请号：US11776810
申请日：2007-07-12
IPC分类号： G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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公开(公告)号：US07461209B2
公开(公告)日：2008-12-02
申请号：US11295300
申请日：2005-12-06
申请人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/12
CPC分类号： G06F12/1491 , G06F9/3808 , G06F9/3844 , G06F12/0802 , G06F12/0804 , G06F12/12
摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
摘要翻译： 公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。 瞬态数据存储在处理器本地缓存层次结构中。 附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。 瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。 优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。 提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。 这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。
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公开(公告)号：US20080084777A1
公开(公告)日：2008-04-10
申请号：US11538877
申请日：2006-10-05
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address hits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译： 超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址匹配被转换为N个逻辑真地址位和N个互补地址位。 部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。 这些位组被划分以优化地址解码器中的并行位线的布局。
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公开(公告)号：US07337202B2
公开(公告)日：2008-02-26
申请号：US10745712
申请日：2003-12-24
IPC分类号： G06F15/00
CPC分类号： G06F5/012 , G06F7/5443
摘要： A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and a group of data signals to generate a group of first intermediate signals. The coarse shift stage receives a second set of shift signals and the group of first intermediate signals to generate a group of second intermediate signals and their complement signals. The large shift stage and the coarse shift stage are executed within a first single processor cycle. The negate stage receives a complement decision signal and the group of second intermediate signals along with their complement signals to generate a group of third intermediate signals. Finally, the fine shift stage receives a third set of shift signals and the group of third intermediate signals to generate a group of output signals. The negate stage and the fine shift stage are executed within a second single processor cycle.
摘要翻译： 公开了一种融合乘法加法器电路内的低功率移相和无效单元。 移位和否定单元包括大的移位阶段，粗调班级，否定阶段和精细班级。 大移位级接收第一组移位信号和一组数据信号以产生一组第一中间信号。 粗移位级接收第二组移位信号和第一中间信号组，以产生一组第二中间信号及其补码信号。 在第一单个处理器周期内执行大移位级和粗移位级。 否定阶段接收补码判定信号和第二中间信号组及其补码信号以产生一组第三中间信号。 最后，精细移位级接收第三组移位信号和第三中间信号组，以产生一组输出信号。 否定阶段和精细转换阶段在第二个单个处理器周期内执行。
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