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公开(公告)号：US20090004792A1
公开(公告)日：2009-01-01
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译： 一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层 在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层， 栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠， 通道区域层。
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公开(公告)号：US07666730B2
公开(公告)日：2010-02-23
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译： 一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层 在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层， 栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠， 通道区域层。
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公开(公告)号：US07445981B1
公开(公告)日：2008-11-04
申请号：US11771690
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.
摘要翻译： 一种方法包括在具有第一和第二阱区的半导体层上形成第一栅极电介质层，在第一栅极电介质上方形成第一金属栅电极层，在第一金属栅电极层和相邻侧壁上形成侧壁保护层 的第一栅介质层和第一金属栅极电极层，在第二阱区上形成沟道区，在沟道区上形成第二栅介质层，形成第二栅极电极层，形成第一栅叠层 包括第一阱区域上的第一栅极电介质层和第一金属栅极电极层中的每一个的一部分，并且形成第二栅极堆叠，其包括沟道区域上的第二栅极介电层和第二金属栅极电极层中的每一个的第二栅极堆叠 并在第二个井区域。
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公开(公告)号：US07910442B2
公开(公告)日：2011-03-22
申请号：US11782319
申请日：2007-07-24
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译： 提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。 该方法还包括去除第二层的至少一部分。 该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。 该方法还包括完成半导体器件的形成。
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公开(公告)号：US20090029538A1
公开(公告)日：2009-01-29
申请号：US11782319
申请日：2007-07-24
IPC分类号： H01L21/302 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译： 提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。 该方法还包括去除第二层的至少一部分。 该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。 该方法还包括完成半导体器件的形成。
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公开(公告)号：US20090068807A1
公开(公告)日：2009-03-12
申请号：US11851719
申请日：2007-09-07
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823412 , H01L21/823807 , H01L21/823857
摘要： A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon.
摘要翻译： 提供了一种形成包括在半导体衬底中形成第一区域和第二区域的器件的方法。 所述方法还包括在所述第一区域上形成半导体材料，其中所述半导体材料具有与所述第一半导体衬底不同的电性质，在所述第一区域上形成第一电介质材料，在所述第一介电材料上沉积第二电介质材料， 所述第二区域，其中所述第二介电材料不同于所述第一介电材料，以及在所述高介电常数材料上沉积栅电极材料。 在一个实施例中，半导体材料是硅锗，并且半导体衬底是硅。
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公开(公告)号：US07709331B2
公开(公告)日：2010-05-04
申请号：US11851719
申请日：2007-09-07
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823412 , H01L21/823807 , H01L21/823857
摘要： A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon.
摘要翻译： 提供了一种形成包括在半导体衬底中形成第一区域和第二区域的器件的方法。 所述方法还包括在所述第一区域上形成半导体材料，其中所述半导体材料具有与所述第一半导体衬底不同的电性质，在所述第一区域上形成第一电介质材料，在所述第一介电材料上沉积第二电介质材料， 所述第二区域，其中所述第二介电材料不同于所述第一介电材料，以及在所述高介电常数材料上沉积栅电极材料。 在一个实施例中，半导体材料是硅锗，并且半导体衬底是硅。
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公开(公告)号：US09362280B2
公开(公告)日：2016-06-07
申请号：US13893026
申请日：2013-05-13
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238 , H01L29/10
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
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公开(公告)号：US08460996B2
公开(公告)日：2013-06-11
申请号：US11931565
申请日：2007-10-31
IPC分类号： H01L21/8242
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。
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公开(公告)号：US20130249015A1
公开(公告)日：2013-09-26
申请号：US13893026
申请日：2013-05-13
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
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