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公开(公告)号：US20090004792A1
公开(公告)日：2009-01-01
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译： 一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层 在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层， 栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠， 通道区域层。
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公开(公告)号：US07910442B2
公开(公告)日：2011-03-22
申请号：US11782319
申请日：2007-07-24
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译： 提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。 该方法还包括去除第二层的至少一部分。 该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。 该方法还包括完成半导体器件的形成。
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公开(公告)号：US07666730B2
公开(公告)日：2010-02-23
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译： 一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层 在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层， 栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠， 通道区域层。
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公开(公告)号：US20090029538A1
公开(公告)日：2009-01-29
申请号：US11782319
申请日：2007-07-24
IPC分类号： H01L21/302 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译： 提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。 该方法还包括去除第二层的至少一部分。 该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。 该方法还包括完成半导体器件的形成。
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公开(公告)号：US07445981B1
公开(公告)日：2008-11-04
申请号：US11771690
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.
摘要翻译： 一种方法包括在具有第一和第二阱区的半导体层上形成第一栅极电介质层，在第一栅极电介质上方形成第一金属栅电极层，在第一金属栅电极层和相邻侧壁上形成侧壁保护层 的第一栅介质层和第一金属栅极电极层，在第二阱区上形成沟道区，在沟道区上形成第二栅介质层，形成第二栅极电极层，形成第一栅叠层 包括第一阱区域上的第一栅极电介质层和第一金属栅极电极层中的每一个的一部分，并且形成第二栅极堆叠，其包括沟道区域上的第二栅极介电层和第二金属栅极电极层中的每一个的第二栅极堆叠 并在第二个井区域。
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6.发明授权Process for forming an electronic device including a transistor having a metal gate electrode 失效用于形成包括具有金属栅电极的晶体管的电子器件的工艺公开(公告)号：US07750374B2
公开(公告)日：2010-07-06
申请号：US11559633
申请日：2006-11-14
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译： 电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。 在一个实施例中，第一功函数小于半导体层的价带。 在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。 形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。 具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。
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7.发明申请ELECTRONIC DEVICE INCLUDING A TRANSISTOR HAVING A METAL GATE ELECTRODE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 失效包括具有金属栅电极的晶体管的电子器件和用于形成电子器件的工艺公开(公告)号：US20080111155A1
公开(公告)日：2008-05-15
申请号：US11559633
申请日：2006-11-14
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译： 电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。 在一个实施例中，第一功函数小于半导体层的价带。 在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。 形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。 具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。
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公开(公告)号：US06218302B1
公开(公告)日：2001-04-17
申请号：US09121068
申请日：1998-07-21
申请人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
发明人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76882 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552 , H01L2924/013 , H01L2924/0105 , H01L2924/01026
摘要： An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
摘要翻译： 互连（60）形成在衬底（10）上。 在一个实施例中，将覆盖在衬底（10）上的粘合/阻挡层（81），铜合金晶种层（42）和铜膜（43）沉积，并且将衬底（10）退火。 在替代实施例中，在衬底上沉积铜膜，并对铜膜进行退火。 在另一个实施例中，在基板（10）上沉积粘合/阻挡层（81），种子层（82），导电膜（83）和铜合金封盖膜（84），以形成互连 （92）。 沉积和退火步骤可以在公共处理平台上进行。
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公开(公告)号：US20060267113A1
公开(公告)日：2006-11-30
申请号：US11140161
申请日：2005-05-27
申请人： Philip Tobin , Cristiano Capasso
发明人： Philip Tobin , Cristiano Capasso
IPC分类号： H01L29/76
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A device structure and method for forming the device structure has a semiconductor substrate with an overlying first metal oxide layer, an overlying intermediate layer with a first metal and either nitrogen or carbon, and an overlying second metal oxide layer. Oxygen is then provided to the intermediate layer. The oxygen has the effect of changing the intermediate layer from a conducting layer to a dielectric layer. A final device may then be formed, for example, by forming a gate and two current electrodes.
摘要翻译： 用于形成器件结构的器件结构和方法具有具有覆盖的第一金属氧化物层的半导体衬底，具有第一金属和氮或碳的上覆中间层以及覆盖的第二金属氧化物层。 然后将氧气提供给中间层。 氧具有将中间层从导电层改变为电介质层的效果。 然后可以例如通过形成栅极和两个电流电极来形成最终器件。
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