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公开(公告)号：US08593170B2
公开(公告)日：2013-11-26
申请号：US12891658
申请日：2010-09-27
IPC分类号： G01R31/02 , G01R31/26 , G01R27/28 , H03K19/003 , H03K19/00
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译： 公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。 一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。 第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。 第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。 第一TSV和第二TSV之间的电连接在第二管芯的外部。 在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。
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公开(公告)号：US20110102011A1
公开(公告)日：2011-05-05
申请号：US12891658
申请日：2010-09-27
IPC分类号： G01R31/26 , H01L23/528
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译： 公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。 一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。 第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。 第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。 第一TSV和第二TSV之间的电连接在第二管芯的外部。 在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。
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公开(公告)号：US20120025841A1
公开(公告)日：2012-02-02
申请号：US13194861
申请日：2011-07-29
申请人： Jaemin Kim , Geert Van der Plas , Paul Marchal
发明人： Jaemin Kim , Geert Van der Plas , Paul Marchal
IPC分类号： G01R31/02
CPC分类号： G01R27/2605 , G01R31/2853
摘要： A measurement system for determining the capacitance of a device-under-test in an integrated circuit is disclosed. In one aspect, the measurement system has a reference circuit and a test circuit. Each circuit has first and second diodes that are switched in accordance with a clock cycle to charge and discharge the associated circuit. A method takes average current measurements for each circuit at one voltage level and processes them so that the capacitance of a device-under-test connected to the test circuit can accurately and reliably be determined. Two voltage levels may be used and adjustments are made for voltage threshold of the diodes and also their resistance.
摘要翻译： 公开了一种用于确定集成电路中被测器件的电容的测量系统。 在一个方面，测量系统具有参考电路和测试电路。 每个电路具有根据时钟周期来切换以对相关电路进行充电和放电的第一和第二二极管。 一种方法在一个电压电平下对每个电路进行平均电流测量，并对它们进行处理，从而可以准确可靠地确定连接到测试电路的被测器件的电容。 可以使用两个电压电平，并且对二极管的电压阈值以及它们的电阻进行调整。
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4.发明授权公开(公告)号：US08773157B2
公开(公告)日：2014-07-08
申请号：US13174617
申请日：2011-06-30
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31717 , H01L22/34
摘要： A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.
摘要翻译： 公开了在每个制造阶段在三维集成电路（IC）中测试穿硅通孔（TSV）的测试电路和方法。 在一个方面，该方法包括测试每个单独的TSV，TSV未测试中的TSV测试之间的短路，以及紧邻的TSV之间的短路以及TSV未测试之间的连接以及 ICs。 测试电路具有通过上拉电阻连接到电源的三个可切换电流路径，并且切换：校准路径，短路径和电流测量路径。 电源连接到测量路径，校准路径和短路通过相应的下拉电阻连接到地。 对于每个TSV低于测试，通过关闭开关的不同组合来选择所需的操作模式。 在每种运行模式下流过上拉电阻的电流表示TSV未测试是否已通过或失败。
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公开(公告)号：US20130002272A1
公开(公告)日：2013-01-03
申请号：US13174617
申请日：2011-06-30
IPC分类号： G01R31/02
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31717 , H01L22/34
摘要： A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.
摘要翻译： 公开了在每个制造阶段在三维集成电路（IC）中测试穿硅通孔（TSV）的测试电路和方法。 在一个方面，该方法包括测试每个单独的TSV，TSV未测试中的TSV测试之间的短路，以及紧邻的TSV之间的短路以及TSV未测试之间的连接以及 ICs。 测试电路具有通过上拉电阻连接到电源的三个可切换电流路径，并且切换：校准路径，短路径和电流测量路径。 电源连接到测量路径，校准路径和短路通过相应的下拉电阻连接到地。 对于每个TSV低于测试，通过关闭开关的不同组合来选择所需的操作模式。 在每种运行模式下流过上拉电阻的电流表示TSV未测试是否已通过或失败。
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6.发明授权公开(公告)号：US07552304B2
公开(公告)日：2009-06-23
申请号：US11133155
申请日：2005-05-18
IPC分类号： G06F12/02
CPC分类号： G06F8/4432 , G06F8/4442 , Y02D10/41
摘要： Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.
摘要翻译： 描述了用于分层存储器的设计时数据分配技术的方法，装置和软件产品，例如基本上数字系统中的多存储器存储器以及用于这种存储器的运行时存储器管理技术的方法，装置和软件产品 系统。 描述内存分配技术，用于将数据分配给分层存储器，特别是对于在运行时分配动态创建/删除的任务的数据的多任务应用程序。 分层存储器（诸如多存储器存储器）的能量消耗在很大程度上取决于数据如何被分配给存储器组。 描述了分层存储器的设计时数据分配技术的方法，装置和软件产品，例如基本上数字系统中的多存储存储器，其提高诸如能量消耗的成本函数。
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公开(公告)号：US07234126B2
公开(公告)日：2007-06-19
申请号：US09935789
申请日：2001-08-22
申请人： Francky Catthoor , Peng Yang , Chun Wong , Paul Marchal , Aggeliki Prayati , Nathalie Cossement , Rudy Lauwereins
发明人： Francky Catthoor , Peng Yang , Chun Wong , Paul Marchal , Aggeliki Prayati , Nathalie Cossement , Rudy Lauwereins
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/86
摘要： A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
摘要翻译： 一种设计数字系统的系统和方法。 本发明的一个方面包括一种用于设计基本数字系统的方法，其中执行基于Pareto的任务并发优化。 该方法使用数字系统的功能和时序的系统级描述。 系统级描述包括多个任务。 在所述系统级描述上执行任务并发优化，从而获得包含Pareto类任务优化信息的任务并发优化系统级描述。 本质上数字系统是基于所述任务并发优化的系统级描述而设计的。 在本发明的一个实施例中，描述包括基本数字系统的“灰盒”描述。
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公开(公告)号：US4523884A
公开(公告)日：1985-06-18
申请号：US309604
申请日：1981-10-08
申请人： Gilles Clement , Daniel Francois , Paul Marchal , Claude Moreau
发明人： Gilles Clement , Daniel Francois , Paul Marchal , Claude Moreau
CPC分类号： B25J5/02 , B25J18/025 , B25J19/0029 , B25J21/00 , Y10S414/122
摘要： Remote manipulating assembly of the type comprising a movable platform carrying a telescopic supporting or carrying assembly at the end of which a remote manipulation arm can be displaced within an enclosure, wherein the platform is located within a wall of the enclosure, at least one opening being provided in the wall to permit the introduction of the telescopic carrying assembly of axis AA into the enclosure, and wherein the platform is provided with a hood within which the telescopic carrying assembly and the remote manipulation arm can be completely contained, the hood also being provided in its opening part with means for the tight connection to the wall of the enclosure cooperating with sealing means provided in the opening, and having at its other end means for controlling the displacements of the telescopic carrying assembly, while also having connection and supply means for the displacements of the remote manipulation arm, together with its operation and the operation of its tools.The invention also relates to a process for connecting a remote manipulation assembly to the opening of an enlcosure.The present remote manipulation assembly is intended for working in hostile or dangerous environments, particularly in the nuclear field.
摘要翻译： 该类型的远程操纵组件包括一个可伸缩的支撑或承载组件的可移动平台，在该终端处远程操纵臂可在外壳内移动，其中平台位于外壳的壁内，至少一个开口 设置在壁中以允许将轴线AA的伸缩式承载组件引入外壳中，并且其中平台设置有罩，可伸缩式携带组件和远程操纵臂可以完全包含在该罩内，罩也被设置 在其开口部分具有用于与设置在开口中的密封装置协作的壳体的紧密连接的装置，并且在其另一端具有用于控制伸缩式承载组件的位移的装置，同时还具有连接和供应装置， 远程操纵臂的位移，以及其操作及其操作 喔。 本发明还涉及一种用于将远程操作组件连接到放大器的开口的过程。 目前的远程操纵组件旨在在敌对或危险的环境中工作，特别是在核领域。
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9.发明授权Apparatus for the separation and recovery of a solid product transported by a gas 失效用于分离和回收由气体输送的固体产物的装置
公开(公告)号：US4261713A
公开(公告)日：1981-04-14
申请号：US65544
申请日：1979-08-10
申请人： Claude Bourdois , Maurice Decolle , Michel Ferard , Paul Marchal , Silviu Vais
发明人： Claude Bourdois , Maurice Decolle , Michel Ferard , Paul Marchal , Silviu Vais
IPC分类号： B65G53/60 , B01D46/00 , B01D46/02 , B01D46/04 , B01D46/06 , B01D46/24 , B01D46/52 , B01D50/00 , B65G53/40 , G21F9/02
CPC分类号： G21F9/02 , B01D46/002 , B01D46/0023 , B01D46/0067 , B01D46/0094 , B01D46/2411 , B01D50/00 , B01D2265/06 , Y10S55/09
摘要： Apparatus for the separation and recovery of a solid product transported by a gas, wherein said apparatus comprises at least one filter cartridge made from a rigid porous material mounted in a sealed enclosure and defining in the latter a first filter chamber within the at least one cartridge and which communicates by its lower end with a tube for the collection of the separated solid product and a second chamber for the collection of the filtered gas outside the said at least one cartridge, the latter having two large-surface opposite porous walls maintained with an appropriate spacing by spacers fixed on the said walls and disposed in the filter chamber in such a way as to form deflectors, means for introducing the gas transporting the solid product to be separated into the said filter chamber and means for extracting the filtered gas from the collection chamber.
摘要翻译： 用于分离和回收由气体输送的固体产物的装置，其中所述装置包括至少一个由刚性多孔材料制成的滤筒，该刚性多孔材料安装在密封的壳体中，并在其中限定在所述至少一个筒体内的第一过滤室 并且其下端与用于收集分离的固体产物的管连通，以及用于在所述至少一个筒的外部收集被过滤的气体的第二室，后者具有两个保持有 通过间隔件固定在所述壁上并以这样的方式设置在过滤室中以形成偏转器的适当间隔，用于将输送待分离的固体产物的气体引入到所述过滤室中的装置，以及用于从所述过滤室中提取过滤气体的装置 收集室。
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公开(公告)号：US20090112344A1
公开(公告)日：2009-04-30
申请号：US12258261
申请日：2008-10-24
申请人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
发明人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
IPC分类号： G06F19/00
CPC分类号： G06F17/5068
摘要： A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric.
摘要翻译： 公开了一种用于优化设备的设计的方法。 相对于预定的度量，例如， 设备速度，面积，功耗或产量。 在一个方面，该方法包括获得设备的设计。 该设计包括设计组件。 该方法还包括从设计组件确定与第二设计组件相比具有比预定度量更高的灵敏度的至少一组第一设计组件。 第一个设计组件可能在设计的关键路径上。 该方法还包括调整第一设计组件和用于制造第一设计组件的技术，从而减少第一设计组件的可变性并获得关于预定度量的优化设计。
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