公开(公告)号：US06959279B1

公开(公告)日：2005-10-25

申请号：US10108766

申请日：2002-03-26

申请人： Geoffrey Bruce Jackson ,  Aditya Raina ,  Bo-Hung Wu ,  Chuan-Shin Rick Lin ,  Ming-Bing Chang ,  Bor-Wen Yang ,  Wen-Kuei Chen ,  Peter J. Holzmann ,  Rodney Lee Doan ,  Saleel V. Awsare

发明人： Geoffrey Bruce Jackson ,  Aditya Raina ,  Bo-Hung Wu ,  Chuan-Shin Rick Lin ,  Ming-Bing Chang ,  Bor-Wen Yang ,  Wen-Kuei Chen ,  Peter J. Holzmann ,  Rodney Lee Doan ,  Saleel V. Awsare

IPC分类号： G10L13/00 ,  G10L13/04

CPC分类号： G10L13/047

摘要： A text-to-speech conversion system that includes a first module to convert text into words, a second module to convert words into phonemes, a third module to map phonemes to sound units, and a storage unit to store speech representations for a library of sound units. The first, second, and third modules and the storage unit are implemented within a single integrated circuit to reduce size and cost. The system typically further includes a ROM to store the codes for the modules, a RAM to store the text and intermediate results, a processor to execute the codes for the modules, a control module to direct the operation of the first, second, and third modules. The storage unit may be implemented with a multi-level, non-volatile analog storage array and may be programmed with a new library of speech representations by a programming module.

摘要翻译： 一种文本转语音转换系统，其包括将文本转换为单词的第一模块，将单词转换为音素的第二模块，将音素映射到声音单元的第三模块，以及存储单元，用于存储语音库 声音单位。 第一，第二和第三模块和存储单元在单个集成电路内实现以减小尺寸和成本。 该系统通常还包括存储用于模块的代码的ROM，用于存储文本和中间结果的RAM，用于执行模块代码的处理器，用于指示第一，第二和第三的操作的控制模块 模块。 存储单元可以用多级非易失性模拟存储阵列实现，并且可以通过编程模块用新的语言表示库进行编程。

公开(公告)号：US06865186B1

公开(公告)日：2005-03-08

申请号：US09501699

申请日：2000-02-10

申请人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Ming-Bing Chang ,  Peter Holzmann ,  Oliver Chihkuang Kao ,  Hung-Chuan Pai ,  Carl R. Palmer ,  Aditya Raina

发明人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Ming-Bing Chang ,  Peter Holzmann ,  Oliver Chihkuang Kao ,  Hung-Chuan Pai ,  Carl R. Palmer ,  Aditya Raina

IPC分类号： G06F12/00 ,  G11C7/16 ,  G11C11/56 ,  G11C27/00 ,  H04L12/28

CPC分类号： G11C27/005 ,  G11C7/16 ,  G11C11/5621 ,  G11C2207/16

摘要： A multilevel analog recording and playback system is described. An analog processing circuit processes analog data. A storage circuit includes a non-volatile memory array, a switching circuit, and a communication interface. The non-volatile memory array stores analog and digital data. The switching circuit transfers the analog and digital data to and from the memory array. The communication interface allows a processor to exchange information with the device.

摘要翻译： 描述了多级模拟录音和播放系统。 模拟处理电路处理模拟数据。 存储电路包括非易失性存储器阵列，开关电路和通信接口。 非易失性存储器阵列存储模拟和数字数据。 开关电路将模拟和数字数据传送到存储器阵列和从存储器阵列传送。 通信接口允许处理器与设备交换信息。

公开(公告)号：US06261907B1

公开(公告)日：2001-07-17

申请号：US09453395

申请日：1999-12-03

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11519 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328

摘要： A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further Vcc scaling becomes possible.

摘要翻译： 使用侧壁多晶硅间隔物作为擦除栅极的闪速EEPROM单元。 通过源侧通道热电子注入对单元进行编程，并通过浮动栅极和擦除栅极之间的多晶隧道氧化物进行多对多隧穿扫描。 浮置栅极由在浮栅多自对准蚀刻步骤之前形成的控制栅极侧壁间隔物限定。 在浮栅聚合物的侧壁上生长多晶隧道氧化物之后形成多晶硅侧壁间隔物擦除栅极。 由于多隧道氧化物厚度最小化，所以可以实现具有低功耗的快速编程。 通过使用多重多晶隧道擦除方案，不使用深源结，并可显着减小单元尺寸。 此外，可以同时擦除大扇区的单元，而不需要功耗，并且可以进一步进行Vcc缩放。

公开(公告)号：US5258949A

公开(公告)日：1993-11-02

申请号：US620813

申请日：1990-12-03

申请人： Ko-Min Chang ,  Ming-Bing Chang

发明人： Ko-Min Chang ,  Ming-Bing Chang

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/12 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/12 ,  H01L29/7885

摘要： Programming speed of a nonvolatile memory is improved by enhancing carrier generation. In one form, a nonvolatile memory has a control gate which overlies a channel region in a substrate. A floating gate overlies a portion of the channel region and is positioned between the substrate and the control gate. A source and a drain are formed in the substrate, being displaced by the channel region. A first programming voltage is applied to the drain to create an electric field at a junction between the drain and channel region. Current is forced into the source and through the substrate in order to enhance carrier generation at the junction between the drain and channel region, thereby increasing an electric field at the junction. A second programming voltage, having a ramp shaped leading edge, is applied to the control gate to increase the electrical field and to program the memory to a predetermined logic state.

摘要翻译： 通过增强载体生成来提高非易失性存储器的编程速度。 在一种形式中，非易失性存储器具有覆盖在衬底中的沟道区域的控制栅极。 浮动栅极覆盖沟道区的一部分并位于衬底和控制栅之间。 源极和漏极形成在衬底中，被沟道区域置换。 将第一编程电压施加到漏极，以在漏极和沟道区域之间的结处产生电场。 电流被迫进入源极并通过衬底，以便增强在漏极和沟道区域之间的结处的载流子产生，从而增加了结处的电场。 具有斜坡形状的前沿的第二编程电压被施加到控制栅极以增加电场并将存储器编程到预定的逻辑状态。

公开(公告)号：US06563733B2

公开(公告)日：2003-05-13

申请号：US09866537

申请日：2001-05-24

申请人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

发明人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

IPC分类号： G11C1604

CPC分类号： H01L29/511 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.

摘要翻译： 半导体存储器包括沿行和列布置的多个存储单元，每个单元具有浮置栅极，漏极区域，源极区域，程序栅极端子和选择栅极端子。 沿着每行单元的单元的程序栅极端子连接在一起形成连续的程序栅极线。 沿着每行单元的单元的选择栅极端子连接在一起形成连续的选择栅极线。 沿着每行单元格的单元格的源区域连接在一起形成连续的源极线。 沿着每列的单元被分成预定数量的组，并且每个组中的单元的漏极区域连接到跨越单元组中的单元格延伸的局部位线。 全局位线沿着每两列单元格延伸，并且被配置为选择性地提供沿着相应的两列单元格的本地位线的电连接。 每个单元的浮置栅极来自第一层多晶硅，编程栅极线来自第二多晶硅层，选择栅极线来自第三多晶硅层，源极线是扩散线。

公开(公告)号：US5991204A

公开(公告)日：1999-11-23

申请号：US72924

申请日：1998-05-05

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423

CPC分类号： G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328

摘要： A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

摘要翻译： 使用侧壁多晶硅间隔物作为擦除栅极的闪速EEPROM单元。 通过源侧通道热电子注入对单元进行编程，并通过浮动栅极和擦除栅极之间的多晶隧道氧化物进行多对多隧穿扫描。 浮置栅极由在浮栅多自对准蚀刻步骤之前形成的控制栅极侧壁间隔物限定。 在浮栅聚合物的侧壁上生长多晶隧道氧化物之后形成多晶硅侧壁间隔物擦除栅极。 由于多隧道氧化物厚度最小化，所以可以实现具有低功耗的快速编程。 通过使用多重多晶隧道擦除方案，不使用深源结，并可显着减小单元尺寸。 此外，可以同时擦除大扇区的单元，而不需要功耗，并且可以进一步进行Vcc缩放。

公开(公告)号：US6125060A

公开(公告)日：2000-09-26

申请号：US383283

申请日：1999-08-26

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11519 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328

摘要： A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

摘要翻译： 使用侧壁多晶硅间隔物作为擦除栅极的闪速EEPROM单元。 通过源侧通道热电子注入对单元进行编程，并通过浮动栅极和擦除栅极之间的多晶隧道氧化物进行多对多隧穿扫描。 浮置栅极由在浮栅多自对准蚀刻步骤之前形成的控制栅极侧壁间隔物限定。 在浮栅聚合物的侧壁上生长多晶隧道氧化物之后形成多晶硅侧壁间隔物擦除栅极。 由于多隧道氧化物厚度最小化，所以可以实现具有低功耗的快速编程。 通过使用多重多晶隧道擦除方案，不使用深源结，并可显着减小单元尺寸。 此外，可以同时擦除大扇区的单元，而不需要功耗，并且可以进一步进行Vcc缩放。

公开(公告)号：US5705439A

公开(公告)日：1998-01-06

申请号：US635826

申请日：1996-04-22

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： A method for forming an asymmetrical LDD structure is described. A polysilicon gate electrode is formed overlying a layer of gate silicon oxide on the surface of a semiconductor substrate. The surfaces of the semiconductor substrate and the gate electrode are oxidized to form a surface oxide layer. Polysilicon spacers are formed on the sidewalls of the gate electrode wherein one side of the gate electrode is a source side and the other side of the gate electrode is a drain side. The polysilicon spacer on the source side of the gate electrode is removed. First ions are implanted to form heavily doped source and drain regions within the semiconductor substrate not covered by the gate electrode and the polysilicon spacer on the drain side of the gate electrode. Then the drain side polysilicon spacer is removed. Second ions are implanted to form a lightly doped drain region within the semiconductor substrate underlying the removed drain side polysilicon spacer completing the formation of a lightly doped drain structure in the fabrication of an integrated circuit device.

摘要翻译： 描述了形成不对称LDD结构的方法。 在半导体衬底的表面上形成覆盖一层栅极氧化硅的多晶硅栅电极。 半导体衬底和栅电极的表面被氧化形成表面氧化层。 多晶硅间隔物形成在栅电极的侧壁上，其中栅电极的一侧为源极侧，栅电极的另一侧为漏极侧。 去除栅电极的源极侧的多晶硅间隔物。 注入第一离子以在半导体衬底内形成不被栅极电极和栅电极漏极侧的多晶硅间隔物覆盖的重掺杂源极和漏极区域。 然后去除漏极侧多晶硅间隔物。 注入第二离子，以在去除的漏极侧多晶硅间隔物下面的半导体衬底内形成轻掺杂的漏极区，从而在集成电路器件的制造中完成轻掺杂漏极结构的形成。

公开(公告)号：US5644532A

公开(公告)日：1997-07-01

申请号：US432822

申请日：1995-05-02

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

CPC分类号： H01L29/7883 ,  G11C16/0491 ,  H01L27/115

摘要： A selected cell in a virtual-ground flash EEPROM array, which is based on a source-coupled, split-gate storage cell, is programmed by grounding the source bit line of the selected cell, grounding the drain bit line of the immediately adjacent cell which shares the same source bit line, applying a write bias voltage to the remaining bit lines, applying a programming voltage to the word line associated with the selected cell, and applying ground to the remaining word lines.

摘要翻译： 基于源极耦合的分离栅极存储单元的虚拟地闪存EEPROM阵列中的选定单元通过将所选择的单元的源极线接地来编程，使紧邻的单元的漏极位线接地 其共享相同的源位线，向剩余的位线施加写入偏置电压，将编程电压施加到与所选择的单元相关联的字线，以及将地对其余字线施加。

公开(公告)号：US5612240A

公开(公告)日：1997-03-18

申请号：US663439

申请日：1996-06-13

申请人： Ming-Bing Chang

发明人： Ming-Bing Chang

IPC分类号： H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/28 ,  H01L21/823475 ,  Y10S438/947

摘要： A method was achieved for making electrical connections to FET self-aligned source/drain areas extending the limits of the photolithographic resolution and relaxing the alignment tolerance. FET gate electrodes are formed by patterning a first polysilicon layer having a first insulating layer thereon. Lightly doped drains (LDDs) and insulating first sidewall spacers are then formed. A polycide layer (second polysilicon/silicide layer) having a second insulating thereon is then deposited and patterned. The new method involves etching the second insulating layer and partially into the polycide layer. After removing the photoresist, another dielectric layer is conformally deposited and then anisotropically etched back to form the second sidewall spacers. The remaining polycide layer is then etched using the second insulating layer and the second spacer as a hard mask. Thus, second poly extensions are formed over and onto the first poly and the field oxide. Using this new process, both the second polysilicon layer and the contact layer become alignment insensitive and silicon trenches, caused by misalignment, cannot occur. Furthermore, a minimum gate length, a minimum gate to FOX spacing and a minimum FOX isolation width can be achieved with the existing 0.35 um process technology.

摘要翻译： 实现了与FET自对准源极/漏极区域的电连接的方法，延伸了光刻分辨率的极限并且放宽了对准公差。 通过对其上具有第一绝缘层的第一多晶硅层进行构图来形成FET栅电极。 然后形成轻掺杂的漏极（LDD）和绝缘的第一侧壁间隔物。 然后沉积并图案化具有第二绝缘层的多晶硅化物层（第二多晶硅/硅化物层）。 该新方法涉及蚀刻第二绝缘层并部分地进入多晶硅化物层。 在去除光致抗蚀剂之后，另外介电层被共形沉积，然后各向异性地回蚀以形成第二侧壁间隔物。 然后使用第二绝缘层和第二间隔物作为硬掩模蚀刻剩余的多晶硅化物层。 因此，在第一多晶氧化物和场氧化物上形成第二多晶延伸。 使用这种新工艺，第二多晶硅层和接触层都变为对准不敏感，并且不会发生由未对准引起的硅沟槽。 此外，使用现有的0.35um工艺技术，可以实现最小栅极长度，最小栅极至FOX间距和最小FOX隔离宽度。