公开(公告)号：US07265069B2

公开(公告)日：2007-09-04

申请号：US11211133

申请日：2005-08-24

申请人： George E. Sakoske ,  Kenneth R. Ackerman ,  John M. Bauer

发明人： George E. Sakoske ,  Kenneth R. Ackerman ,  John M. Bauer

IPC分类号： C03C6/00 ,  C03C6/06 ,  C03C6/08

CPC分类号： C03B27/012 ,  C03B32/00 ,  C03C1/026 ,  C03C1/04 ,  C03C1/105

摘要： The invention provides an opalescent forehearth color concentrate comprising a non-smelted agglomerated interspersion of particles for use in coloring glass, said concentrate comprising by weight from about 10% to about 70% of a glass component and from about 30% to about 90% of one or more opalescent pigments, the glass component comprising by weight from about 10% to about 50% ZnO and about 15 to about 60% SiO2. The invention also provides a method of using the color concentrate.

公开(公告)号：US07737062B2

公开(公告)日：2010-06-15

申请号：US11758273

申请日：2007-06-05

申请人： George E. Sakoske ,  Kenneth R. Ackerman ,  John M. Bauer

发明人： George E. Sakoske ,  Kenneth R. Ackerman ,  John M. Bauer

IPC分类号： C03C6/00 ,  C03C6/06 ,  C03C6/08

CPC分类号： C03B27/012 ,  C03B32/00 ,  C03C1/026 ,  C03C1/04 ,  C03C1/105

摘要： The invention provides an opalescent forehearth color concentrate comprising a non-smelted agglomerated interspersion of particles for use in coloring glass, said concentrate comprising by weight from about 10% to about 70% of a glass component and from about 30% to about 90% of one or more opalescent pigments, the glass component comprising by weight from about 10% to about 50% ZnO and about 15 to about 60% SiO2. The invention also provides a method of using the color concentrate.

摘要翻译： 本发明提供了一种乳白色前浊颜色浓缩物，其包含用于着色玻璃的颗粒的非熔融聚集的间隙，所述浓缩物包含约10％至约70％的玻璃组分和约30％至约90％的玻璃组分 一种或多种乳白色颜料，所述玻璃组分包含约10％至约50％的ZnO和约15至约60％的SiO 2。 本发明还提供了一种使用浓缩色料的方法。

公开(公告)号：US5604753A

公开(公告)日：1997-02-18

申请号：US177861

申请日：1994-01-04

申请人： John M. Bauer ,  Glenn J. Hinton ,  Gregory P. Meece ,  David B. Papworth

发明人： John M. Bauer ,  Glenn J. Hinton ,  Gregory P. Meece ,  David B. Papworth

IPC分类号： G06F11/10

CPC分类号： G06F11/1064

摘要： A method and apparatus for performing error correction on data from an external memory is described. The present invention includes a method and apparatus for receiving data from an external memory source and determining if the data has an error. The data is forwarded to the requesting unit while the error correction is performed on the data, such that the two operations are performed in parallel.The present invention also includes a method and apparatus for subsequently correcting data if a single bit error exists. The corrected data is then forwarded to the requesting unit during the next cycle. Also if an error is detected, the present invention produces an indication to the device. The device is flushed in response to the indication.

摘要翻译： 描述用于对来自外部存储器的数据执行纠错的方法和装置。 本发明包括用于从外部存储器源接收数据并确定数据是否具有错误的方法和装置。 在对数据执行错误校正的同时将数据转发到请求单元，使得并行执行两个操作。 本发明还包括如果存在单个位错误则用于随后校正数据的方法和装置。 然后在下一个周期中将修正的数据转发到请求单元。 此外，如果检测到错误，则本发明产生对该装置的指示。 响应于指示，将设备刷新。

公开(公告)号：US5701503A

公开(公告)日：1997-12-23

申请号：US360331

申请日：1994-12-21

申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831

摘要： A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer. When the processor has transferred the entire cache line to the L2 cache memory, the processor signals the L2 cache memory to transfer the contents of the chunk write buffer into the data array of the cache memory.

摘要翻译： 一种利用块写入缓冲器在处理器和存储器系统之间传送信息的方法和装置，其中对L2高速缓冲存储器的读取和写入请求由处理器控制。 与每个这样的请求相关联的高速缓存行大于耦合L2高速缓冲存储器和处理器的接口。 读取请求以突发方式从L2高速缓冲存储器返回到处理器。 在处理器不需要读取请求的接口的时钟周期期间，写入请求从处理器传送到L2高速缓冲存储器。 写请求不需要以突发方式传输; 相反，与被称为块的接口的大小相对应的写入请求的一部分从处理器传送到L2高速缓冲存储器，并临时存储在块写入缓冲器中。 当处理器将整个高速缓存行传输到L2高速缓冲存储器时，处理器发信号通知L2缓存存储器，以将块写入缓冲器的内容传送到高速缓冲存储器的数据阵列中。

公开(公告)号：US07158911B2

公开(公告)日：2007-01-02

申请号：US10821822

申请日：2004-04-09

申请人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

发明人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

IPC分类号： H01L31/58

CPC分类号： G06F1/206 ,  G01K7/015 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16 ,  Y02D10/172

摘要： An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

摘要翻译： 集成的片上热管理系统，提供IC器件的闭环温度控制和执行IC器件热管理的方法。 热管理系统包括温度检测元件，功率调制元件，控制元件和可见度元件。 温度检测元件包括用于检测管芯温度的温度传感器。 功率调制元件可以通过直接降低IC器件的功耗来限制IC器件执行指令的速度，通过限制由IC器件执行的指令的数量，或通过 这些技术的组合。 控制元件允许控制热管理系统的行为，并且可见性元件允许外部设备监视热管理系统的状态。

公开(公告)号：US5921492A

公开(公告)日：1999-07-13

申请号：US524614

申请日：1995-09-07

申请人： John M. Bauer

发明人： John M. Bauer

IPC分类号： A01K89/016 ,  A01K89/015

CPC分类号： A01K89/016

摘要： A fly fishing reel having a large diameter arbor wall defining a large diameter recess within the spool within which recess are contained support structure for rotatably supporting the spool, and a digitally manipulable drag adjustment knob rotatably actuable through use of a single finger to apply a rotary adjusting moment on the knob. Also enclosed within the large diameter central recess of the reel is a zero backlash drag engagement structure operable to eliminate line jerk and to control the direction of rotation of the spool, thus enabling customizing of the reel for right or left handed fishermen.

摘要翻译： 一种具有大直径心轴壁的飞钓钓鱼卷轴，其在所述卷轴内限定有大直径的凹部，在所述卷轴内容纳有所述凹部的支撑结构，所述支撑结构用于可旋转地支撑所述卷轴;以及数字可操纵的拖动调节旋钮，其可旋转地通过使用单个手指致动以施加旋转 调节旋钮上的时刻。 还包围在卷轴的大直径中心凹部内的零间隙拖曳接合结构可操作以消除线路冲击并且控制线轴的旋转方向，从而能够为右手或左手渔民定制卷轴。

公开(公告)号：US5809524A

公开(公告)日：1998-09-15

申请号：US822044

申请日：1997-03-24

申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/123 ,  G06F12/0831

摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

摘要翻译： 一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。 该接口包括地址总线，数据总线和状态总线。 地址总线将请求的地址从控制器传送到高速缓冲存储器。 数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。 状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。 在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。

公开(公告)号：US06980918B2

公开(公告)日：2005-12-27

申请号：US10821292

申请日：2004-04-09

申请人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

发明人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

IPC分类号： G01K7/01 ,  G06F1/20 ,  G06F15/00

CPC分类号： G06F1/206 ,  G01K7/015 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16 ,  Y02D10/172

摘要： An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

摘要翻译： 集成的片上热管理系统，提供IC器件的闭环温度控制和执行IC器件热管理的方法。 热管理系统包括温度检测元件，功率调制元件，控制元件和可见度元件。 温度检测元件包括用于检测管芯温度的温度传感器。 功率调制元件可以通过直接降低IC器件的功耗来限制IC器件执行指令的速度，通过限制由IC器件执行的指令的数量，或者通过 这些技术的组合。 控制元件允许控制热管理系统的行为，并且可见性元件允许外部设备监视热管理系统的状态。

公开(公告)号：US06789037B2

公开(公告)日：2004-09-07

申请号：US09784255

申请日：2001-02-14

申请人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

发明人： Stephen H. Gunther ,  Frank Binns ,  Jack D. Pippin ,  Linda J. Rankin ,  Edward A. Burton ,  Douglas M. Carmean ,  John M. Bauer

IPC分类号： G01K710

CPC分类号： G06F1/206 ,  G01K7/015 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16 ,  Y02D10/172

摘要： An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

公开(公告)号：US5715428A

公开(公告)日：1998-02-03

申请号：US639719

申请日：1996-04-29

申请人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

发明人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions. State transitions depend on both processor generated activities and activities by other bus agents, including other processors. Data consistency is guaranteed in systems having multiple levels of cache and shared memory and/or multiple active agents, such that no agent ever reads stale data and actions are serialized as needed.

摘要翻译： 一种计算机系统，包括具有高速缓存层级的多个高速缓存代理，所述高速缓存代理器通过系统总线共享存储器并根据协议发出存储器访问请求，其中高速缓存行具有包括多条线路之一的当前状态 状态。 多个行状态包括修改的（M）状态，其中M状态的第一高速缓存代理的行具有比系统中的任何其他副本更新的数据; 排除（E）状态，其中第一高速缓存代理中的E状态中的线是系统中唯一具有高速缓存行中的数据的副本的代理，第一高速缓存代理将数据修改为 所述高速缓存行独立于耦合到所述系统总线的其它所述代理; 共享（S）状态，其中S状态的行指示多于一个代理具有该行中的数据的副本; 和指示该行不存在于缓存中的无效（I）状态。 对I状态的行进行读取或写入会导致高速缓存未命中。 本发明将状态与线相关联并且定义了管理状态转换的规则。 状态转换取决于处理器生成的活动和其他总线代理（包括其他处理器）的活动。 在具有多级缓存和共享内存和/或多个活动代理的系统中保证数据一致性，使得任何代理程序都不会读取过时的数据，并且操作根据需要进行序列化。