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1.发明授权Data processing system and method for generating memory control signals with clock skew tolerance 失效用于产生具有时钟偏差容限的存储器控制信号的数据处理系统和方法
公开(公告)号：US5870349A
公开(公告)日：1999-02-09
申请号：US959653
申请日：1997-10-28
IPC分类号： G11C7/10 , G11C11/412 , G11C7/00
CPC分类号： G11C7/1075 , G11C11/412
摘要： The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations a and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
摘要翻译： 本发明的数据处理系统实现了一个多端口存储单元，其中端口功能基于它们可被访问的定时周期被划分。 例如，在一种情况下，第一端口可以仅用于读取操作，并且仅在定时周期的第一部分期间被访问。 类似地，第二端口可以用于读取或写入操作a，并且可以仅在定时周期的第二部分期间被访问。 为了确保多端口存储单元功能正常，两个端口都不应同时访问。 实现电路和方法以通过以独特且有用的方式实现延迟功能来确保两个端口不被同时访问。
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2.发明授权Data processing system and method for implementing a multi-port memory cell 失效用于实现多端口存储单元的数据处理系统和方法
公开(公告)号：US5956286A
公开(公告)日：1999-09-21
申请号：US958559
申请日：1997-10-28
CPC分类号： G11C8/16
摘要： The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
摘要翻译： 本发明的数据处理系统实现了一个多端口存储单元，其中端口功能基于它们可被访问的定时周期被划分。 例如，在一种情况下，第一端口可以仅用于读取操作，并且仅在定时周期的第一部分期间被访问。 类似地，第二端口可以用于读取或写入操作，并且可以仅在定时周期的第二部分期间被访问。 为了确保多端口存储单元功能正常，两个端口都不应同时访问。 实现电路和方法以通过以独特且有用的方式实现延迟功能来确保两个端口不被同时访问。
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3.发明授权Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell 失效在多端口存储器单元中用于单时钟，非重叠访问的方法和装置
公开(公告)号：US5907508A
公开(公告)日：1999-05-25
申请号：US959652
申请日：1997-10-28
CPC分类号： G11C8/16
摘要： The data processing system of the present invention implements a multi-port memory cell and control therefor. In response to a single clock signal, the cell is accessed during multiple, non-concurrent intervals during a single clock cycle. Each of the accesses during the clock cycle are over a different line.
摘要翻译： 本发明的数据处理系统实现多端口存储单元并进行控制。 响应于单个时钟信号，在单个时钟周期期间在多个非并发间隔期间访问该单元。 时钟周期内的每个访问都在不同的行上。
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公开(公告)号：US5982692A
公开(公告)日：1999-11-09
申请号：US905000
申请日：1997-08-01
CPC分类号： G11C7/18 , G11C7/1048 , G11C7/12
摘要： A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.
摘要翻译： 提供了一种用于实现具有使用升压放大器配置的性能改善的关键读取路径的存储单元阵列的方法和装置。 存储器位线用升压放大器分成小段，位线连接到放大器的输入。 放大器的输出驱动全局位线。 在“读取”期间，放大器“打开”并在“写入”期间关闭。 在读取期间，一个数组段内的一个存储单元被导通。 存储单元将差分信号驱动到本地位线对上。 此外，在读取期间，启用与本地位线相连的升压放大器。 升压放大器放大输入信号（局部位线对）并将该信号驱动到全局位线。 由于利用升压放大器将位线分解成小段，所以在全局位线上附加了许多升压放大器。 当在全局位线对上产生足够的信号时，全局读出放大器被打开。 因此，位线被快速拉到地，从而显着提高关键读路径的性能。
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公开(公告)号：US5877976A
公开(公告)日：1999-03-02
申请号：US959478
申请日：1997-10-28
摘要： An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density while reducing bitline capacitance of a memory cell. Additionally, the use of vertically separated bitline pairs allows traditional transitional phase relationships between multi-port operations in multi-port memory implementations. To nullify any sensitivity to an overlapping restore operation, this improved topology includes cross-coupled ports.
摘要翻译： 提供了一种用于多端口存储器单元布局的改进的拓扑，其中需要两个或更多位线对来进行数据传输。 位线垂直位移，而不是水平位移。 这种垂直间隔提供了改进的硅密度，同时降低了存储单元的位线电容。 另外，使用垂直分离的位线对允许在多端口存储器实现中的多端口操作之间的传统的过渡相位关系。 为了消除对重复恢复操作的任何敏感性，该改进的拓扑包括交叉耦合端口。
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公开(公告)号：US06915385B1
公开(公告)日：2005-07-05
申请号：US09364449
申请日：1999-07-30
CPC分类号： G06F12/0802 , G06F12/04 , Y02D10/13
摘要： An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.
摘要翻译： 实现了非对齐缓存读取的装置和方法。 将系统总线上的数据信号重新映射到高速缓存行中，其中将以分组方式输出要从高速缓存读取的多个数据值。 重映射定义了缓存行中数据值的分组。 多路复用器耦合到包含数据值的每组存储单元，其中多路复用器输入耦合到相应组中的每个存储单元。 耦合到每个MUX的逻辑阵列产生用于选择从每个MUX输出的数据值的控制信号。 响应于由每个逻辑阵列解码的读地址产生控制信号。
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公开(公告)号：US5963486A
公开(公告)日：1999-10-05
申请号：US100354
申请日：1998-06-19
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).
摘要翻译： 位开关电路（10）包括放大器级（11）和多个输入级（23,33,43,53）。 每个输入级（23,33,43,53）被连接以接收施加到与存储器阵列相关联的位线对的信号作为输入。 每个输入级（23,33,43,53）也与公共节点（24,34,44,54）和选择晶体管（T4，T5，T6，T7）相关联。 每个选择晶体管（T4，T5，T6，T7）响应选择输入信号以将相应的公共节点（24,34,44,54）耦合到地。 这允许读出放大器（11）响应与相应输入级（23,33,43,53）相关联的位线对（20,21,30,31,40,41,50,51）上的数据信号 ）。
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8.发明授权Memory system having a unidirectional bus and method for communicating therewith 失效具有单向总线的存储器系统和与其通信的方法公开(公告)号：US06195280B1
公开(公告)日：2001-02-27
申请号：US09521352
申请日：2000-03-09
IPC分类号： G11C506
CPC分类号： G11C7/1048 , G11C7/12 , G11C7/18
摘要： A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.
摘要翻译： 实现了与其通信的存储器和方法，其具有用于写入多个存储单元组内的存储单元的单向写总线。 与每个存储器单元组相关联的本地位线将写入数据传送到相关联的存储器单元。 耦合到所有存储器单元的全局位线在写操作期间与本地位线分离。 在写操作之后，通过预充电操作来恢复局部位线，在此期间，全局和本地位线也被去耦。
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9.发明授权Memory in a data processing system having uneven cell grouping on bitlines and method therefor 失效在位线上具有不均匀的单元分组的数据处理系统中的存储器及其方法
公开(公告)号：US5892725A
公开(公告)日：1999-04-06
申请号：US78248
申请日：1998-05-13
摘要： A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.
摘要翻译： 实现与其通信的存储器和方法，该存储器具有多个存储单元组。 每个存储单元组包含多个存储单元。 存储器单元组的多个子集的每个子集内的存储单元组包括相同的预定数量的存储器单元。 在读取操作期间，与正在读取数据的存储器单元组相关联的本地位线被耦合到全局位线。 与读取期间未被访问的存储器单元组相关联的其他本地位线与全局位线分离。 读取后，通过预充电操作恢复本地和全局位线。
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公开(公告)号：US5892704A
公开(公告)日：1999-04-06
申请号：US52245
申请日：1998-03-31
CPC分类号： G11C8/08
摘要： A memory array of a plurality of memory cells accessed by either a single-ended wordline or a differential pair of wordlines emanating from a wordline decoder is improved by the inclusion of a sense amplifier circuit on the far end of the memory array from the wordline decoder, which operates to amplify the wordline signals.
摘要翻译： 通过在字线解码器的存储器阵列的远端包括读出放大器电路，可以通过从字线解码器发出的单端字线或字线的差分对访问的多个存储器单元的存储器阵列得到改善 ，其操作以放大字线信号。
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