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19 条记录 (耗时 0.024 秒)

    Methods and apparatus for efficient memory usage
    2.
    发明申请
    Methods and apparatus for efficient memory usage 有权
    用于高效内存使用的方法和设备

    公开(公告)号：US20060106984A1

    公开(公告)日：2006-05-18

    申请号：US10992443

    申请日：2004-11-18

    申请人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

    发明人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

    IPC分类号： G06F12/00

    CPC分类号： G06F12/08 ,  G06F12/0866 ,  G06F2212/205 ,  Y02D10/13

    摘要： In a first aspect, a first method is provided for efficient memory usage. The first method includes the steps of (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种有效的存储器使用的第一种方法。 第一种方法包括以下步骤：（1）确定从第一存储设备检索的数据是否被表征为主要被读取的数据; （2）如果从第一存储设备检索的数据被表征为主要读取的数据（a）将检索的数据写入具有短写入延迟的临时存储设备中; 和（b）将检索的数据写入高密度存储器。 提供了许多其他方面。

    Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces
    3.
    发明申请
    Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces 有权
    动态重构固态存储器件，通过多个数据接口复制和定时复用数据

    公开(公告)号：US20060158917A1

    公开(公告)日：2006-07-20

    申请号：US11035555

    申请日：2005-01-14

    申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Paul Rudrud

    发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Paul Rudrud

    IPC分类号： G11C5/06

    CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/1096 ,  G11C29/022 ,  G11C2029/0409

    摘要： Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.

    摘要翻译： 专用于各个逻辑电路（例如存储器阵列）的多个接口能够被动态地重新配置，以独立运行并行并行地以更集体的方式运行，以确保与所有逻辑电路相关联的数据将被传送，而不管任何 的接口。 具体地，可以动态地重新配置多个接口，每个接口通常被配置为与其他接口并行地传送与相关联的逻辑电路相关联的数据，例如响应于一个或多个接口中检测到的故障， 以时间复用和复制的方式在接口的至少一个子集中的每一个上传送与每个接口相关联的数据。

    Method and apparatus for implementing directory organization to selectively optimize performance or reliability
    4.
    发明申请
    Method and apparatus for implementing directory organization to selectively optimize performance or reliability 有权
    用于实现目录组织以选择性地优化性能或可靠性的方法和装置

    公开(公告)号：US20070168762A1

    公开(公告)日：2007-07-19

    申请号：US11290894

    申请日：2005-11-30

    申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1064 ,  G06F12/082

    摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.

    摘要翻译： 提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。 目录包括用户选择的操作模式，包括演奏模式和可靠性模式。 在可靠性模式下，更多的目录位用于纠错和检测。 在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

    Memory controller and method for handling DMA operations during a page copy
    5.
    发明申请
    Memory controller and method for handling DMA operations during a page copy 失效
    用于在页面复制期间处理DMA操作的存储器控​​制器和方法

    公开(公告)号：US20070083682A1

    公开(公告)日：2007-04-12

    申请号：US11246827

    申请日：2005-10-07

    申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.

    摘要翻译： 存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。 页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。 如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。 如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址 。

    Diagnostic interface architecture for memory device
    6.
    发明申请
    Diagnostic interface architecture for memory device 有权

    公开(公告)号：US20060075282A1

    公开(公告)日：2006-04-06

    申请号：US10955735

    申请日：2004-09-30

    申请人： John Borkenhagen ,  William Hovis ,  James Marcella ,  Paul Rudrud

    发明人： John Borkenhagen ,  William Hovis ,  James Marcella ,  Paul Rudrud

    IPC分类号： G06F11/00

    CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/5602

    摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

    Apparatus and method for handling DMA requests in a virtual memory environment
    7.
    发明申请
    Apparatus and method for handling DMA requests in a virtual memory environment 有权
    用于在虚拟内存环境中处理DMA请求的装置和方法

    公开(公告)号：US20070083681A1

    公开(公告)日：2007-04-12

    申请号：US11246824

    申请日：2005-10-07

    申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

    摘要翻译： 一种装置包括将数据从第一块移动到存储器中的第二块的虚拟存储器管理器。 当虚拟存储器管理器准备好将数据从第一块传送到第二块时，定义第三个临时存储块。 将DMA控制器中的转换表更改为将目标为第一个块的DMA传输指向临时块。 然后，虚拟存储器管理器将数据从第一块传送到第二块。 当传输完成时，检查DMA是否将数据传输到临时块，而第一个块的数据正在写入第二个块。 如果是这样，则将写入临时块的数据写入第二块。 优选地使用硬件寄存器来有效地检测对临时块的改变。

    Autonomic bus reconfiguration for fault conditions
    10.
    发明申请
    Autonomic bus reconfiguration for fault conditions 失效
    自动总线重新配置故障条件

    公开(公告)号：US20050058086A1

    公开(公告)日：2005-03-17

    申请号：US10660217

    申请日：2003-09-11

    申请人： John Borkenhagen ,  Laura Zumbrunnen

    发明人： John Borkenhagen ,  Laura Zumbrunnen

    IPC分类号： G06F11/00 ,  G06F11/20 ,  H04L12/26 ,  H04L12/40

    CPC分类号： G06F11/2005

    摘要： Methods and apparatus are disclosed that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.

    摘要翻译： 公开了允许具有在信令导体上具有故障的信令总线的电子系统以降级的性能来操作的方法和装置。 数据块通过信令总线从第一电子单元传送到第二电子单元。 传输序列使用所有非故障信令导体使用完成传输所需的最小次数发送数据块。