公开(公告)号：US6092422A

公开(公告)日：2000-07-25

申请号：US29894

申请日：1998-03-10

申请人： Gerd K. Binnig ,  Pierre L. Gueret ,  Heinrich Rohrer ,  Peter Vettiger

发明人： Gerd K. Binnig ,  Pierre L. Gueret ,  Heinrich Rohrer ,  Peter Vettiger

IPC分类号： A61F11/00 ,  G01H11/00 ,  G10L11/02 ,  G10L15/28 ,  H04R25/00 ,  G01D21/00

CPC分类号： G01H11/00

摘要： The present invention concerns mechanical signal processing comprising a mechanical adder as a basic building block. Such a mechanical adder (40), which is a basic element of the present invention, comprises a first micromechanical member (40.1) being sensitive to a first frequency (f.sub.1) and a second micromechanical member (40.2) being sensitive to a second frequency (f.sub.2). The two micromechanical members (40.1, 40.2) are coupled via a linear coupling (41) to provide a superposition (sum) of the two frequencies (f.sub.1 and f.sub.2). Based on the adder, AND-gates and OR-gates can be realized by adding further micromechanical members and appropriate linear and non-linear coupling elements.

摘要翻译： PCT No.PCT / IB95 / 00817 Sec。 371日期1998年3月10日 102（e）1998年3月10日PCT PCT 1995年9月29日PCT公布。 公开号WO97 / 13127 日期1997年04月10日本发明涉及机械信号处理，其包括作为基本构建块的机械加法器。 作为本发明的基本元件的这种机械加法器（40）包括对第一频率（f1）敏感的第一微机械构件（40.1）和对第二频率敏感的第二微机械构件（40.2） f2）。 两个微机械构件（40.1,40.2）经由线性耦合（41）耦合以提供两个频率（f1和f2）的叠加（和）。 基于加法器，可以通过添加更多的微机械构件和适当的线性和非线性耦合元件来实现与门和OR门。

公开(公告)号：US4643627A

公开(公告)日：1987-02-17

申请号：US782849

申请日：1985-10-02

申请人： Johannes G. Bednorz ,  Pierre L. Gueret ,  Hermann E. Nievergelt ,  Hanspeter Ott ,  Wolfgang D. Pohl ,  Daniel F. Widmer

发明人： Johannes G. Bednorz ,  Pierre L. Gueret ,  Hermann E. Nievergelt ,  Hanspeter Ott ,  Wolfgang D. Pohl ,  Daniel F. Widmer

IPC分类号： G01R31/26 ,  B25J9/02 ,  C23C14/56 ,  C23F4/00 ,  G12B5/00 ,  H01L21/02 ,  H01L21/677 ,  H01L21/68

CPC分类号： H01L21/67196 ,  H01L21/67742 ,  Y10S414/139 ,  Y10T74/18992

摘要： A vacuum transfer device includes a central processing chamber and a plurality of additional chambers radially positioned around the central chamber and in vacuum-tight connection therewith. A rotatable coulisse arrangement in the central chamber is extendable so as to reach into the additional chambers when correctly aligned. The device can transfer objects among several work stations without intermediate venting and re-evacuation of the system of chambers.

摘要翻译： 真空传送装置包括中央处理室和围绕中心室径向定位并与其真空密封连接的多个附加室。 中心室中的可旋转的肠胃排列可以延伸，以便在正确对准时进入附加室。 该设备可以在多个工作站之间传送物体，而不会对室系统进行中等排放和再排放。

公开(公告)号：US3953749A

公开(公告)日：1976-04-27

申请号：US528963

申请日：1974-12-02

申请人： Werner Baechtold ,  Pierre L. Gueret

发明人： Werner Baechtold ,  Pierre L. Gueret

IPC分类号： H03K3/38 ,  H03K19/195

CPC分类号： H03K3/38 ,  H03K19/1952 ,  Y10S505/864

摘要： Two Josephson gates are connected in series to a low impedance voltage source. Each junction is bridged by a load impedance. The feed voltage is maintained in the order of the gap voltage which corresponds to the voltage drop across a Josephson junction when it is in its single-particle-tunneling state. Therefore, only one out of both Josephson elements can exist in the voltage state at a time, and the other junction is forced to assume the superconducting pair-tunneling state.In its symmetric form, the basic circuit can be used as flip-flop or storage means. If asymmetric, the basic circuit shows monostable switching behavior, and it can be used as logic gate. Circuit asymmetry can be caused either by design using different junction areas or electrically by proper bias control currents applied to either or both gates of the basic circuit. The degree of symmetry or asymmetry can even be shifted with electrical means. AND and OR gates and inverting embodiments which perform logic NAND and NOR functions are shown.

摘要翻译： 两个约瑟夫森门串联连接到低阻抗电压源。 每个结都由负载阻抗桥接。 馈电电压保持在间隙电压的顺序，该间隙电压对应于约瑟夫逊结在其单粒子隧穿状态时的电压降。 因此，约瑟夫森元件中只有一个可以一次存在于电压状态，另一个结被强制呈现超导对隧道状态。

公开(公告)号：US4675711A

公开(公告)日：1987-06-23

申请号：US798653

申请日：1985-11-15

申请人： Christoph S. Harder ,  Hans P. Wolf ,  Werner Baechtold ,  Pierre L. Gueret ,  Alexis Baratoff

发明人： Christoph S. Harder ,  Hans P. Wolf ,  Werner Baechtold ,  Pierre L. Gueret ,  Alexis Baratoff

IPC分类号： H01L29/80 ,  H01L29/20 ,  H01L29/205 ,  H01L29/772 ,  H01L29/78 ,  H01L29/12 ,  H01L29/66

CPC分类号： H01L29/772

摘要： The transistor comprises two electrodes, (source (22) and drain (23), with a semiconductor tunnel channel (21A, 21B) arranged therebetween. A gate (24) for applying control signals is coupled to the channel. The semiconductor channel consists of a plurality of regions differing in their current transfer characteristics: contact regions (21c), connected to the source and drain electrodes, and a tunneling region (21t) arranged between the contact regions. The energy of free carriers in the contact regions differs from the energy of the conduction band or the valence band of the tunneling region which forms a low energy tunnel barrier the height (.DELTA.E) of which can be modified by control signals applied to the gate. The operating temperature of the device is kept sufficiently low to have the tunnel current through the barrier outweigh currents of thermionically excited carriers.

摘要翻译： 晶体管包括两个电极（源极（22）和漏极（23）），其间布置有半导体隧道通道（21A，21B），用于施加控制信号的栅极（24）耦合到沟道，半导体通道由 其电流传递特性不同的多个区域：连接到源极和漏极的接触区域（21c）和布置在接触区域之间的隧道区域（21t），接触区域中的自由载流子的能量不同于 形成低能隧道势垒的隧穿区的导带或价带的能量可以通过施加到栅极的控制信号来修改其高度（DELTA E），器件的工作温度保持足够低到 隧道电流通过阻挡层超过热激发载流子的电流。

公开(公告)号：US4647954A

公开(公告)日：1987-03-03

申请号：US654707

申请日：1984-09-27

申请人： Volker Graf ,  Pierre L. Gueret ,  Carl A. Mueller

发明人： Volker Graf ,  Pierre L. Gueret ,  Carl A. Mueller

IPC分类号： H01L29/15 ,  H01L39/22 ,  H01L29/78

CPC分类号： H01L39/228 ,  H01L29/157 ,  Y10S505/86

摘要： The transistor comprises two electrodes, source (12) and drain (13), with a semiconductor tunnel channel (11) arranged therebetween. A gate (14) for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier (some meV) through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage V.sub.G which modifies the barrier height between source and drain thereby changing the tunnel probability.

摘要翻译： 晶体管包括两个电极，源极（12）和漏极（13），其间布置有半导体隧道通道（11）。 用于施加控制信号的门（14）耦合到通道。 半导体在低温下的行为就像具有低势垒（一些meV）的绝缘体，电荷载体可以在所施加的漏极电压的影响下隧穿。 隧道电流可以通过栅极电压VG来控制，栅极电压VG改变源极和漏极之间的势垒高度，从而改变隧道概率。

公开(公告)号：US5360978A

公开(公告)日：1994-11-01

申请号：US941482

申请日：1992-09-08

申请人： Pierre L. Gueret

发明人： Pierre L. Gueret

IPC分类号： G01Q70/06 ,  G01N27/00 ,  G01Q60/16 ,  G01Q70/08 ,  G01Q80/00 ,  G11B9/00 ,  H01J37/26

CPC分类号： G01Q60/16 ,  B82Y35/00 ,  G01Q70/06 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1427 ,  B82Y10/00 ,  G01Q80/00 ,  Y10S977/874

摘要： The multiple STM-tip unit comprises a plurality of individually connectable, electrically separated tunnel tips (52 . . . 54) arranged in a common sandwiched block (5), in the form of a plurality of electrically conducting layers (41, 46, 50) each associated with at least one of said tunnel tips (52 . . . 54) with insulating layers (44, 48) intercalated between said conducting layers (41, 46, 50), the latter each having a contact pad (36, 42, 43) for connection to appertaining electronics. The thickness, area, and material characteristics of said insulating layers (44, 48) are chosen such that the tunnel current through any one of the intercalated insulating layers (44, 48) is negligible with respect to the tunnel current flowing across the gap between the involved tunnel tips (52 . . . 54) and the surface with which said tips cooperate.

摘要翻译： 多个STM-尖端单元包括多个可单独连接的电隔离的隧道末端（52,54），其布置在公共夹块（5）中，呈多个导电层（41,46,50）的形式 ）分别与插入在所述导电层（41,46,50）之间的绝缘层（44,48）中的至少一个所述隧道末端（52,54）相关联，所述绝缘层分别具有接触垫（36,42） ，43）用于连接到电子产品。 选择所述绝缘层（44,48）的厚度，面积和材料特性，使得穿过任何一个插入绝缘层（44,48）的隧道电流相对于流过跨过第 所涉及的隧道尖端（52,54）和所述尖端与其配合的表面。