公开(公告)号：US20100231132A1

公开(公告)日：2010-09-16

申请号：US12719655

申请日：2010-03-08

Applicant: Andrea Logiudice ,  Giorgio Chiozzi

Inventor： Andrea Logiudice ,  Giorgio Chiozzi

IPC: H05B37/02

CPC classification number: H05B33/083 ,  H05B33/0818 ,  H05B33/0827 ,  Y02B20/347

Abstract: A circuit arrangement includes a first light emitting diode and a second light emitting diode emitting light of different colors arranged adjacent to each other for additive color mixing. A first and second controllable current sources are connected to the first and second light emitting diode, respectively, such that the load currents of the light emitting diodes depend on respective control signals received by the current sources. First and second sigma-delta modulators are connected to the first and second light emitting diodes, respectively, and provide bit-streams as control signals to the current sources. The mean value of each bit-stream corresponds to the value of an input signal of the respective sigma-delta modulator.

Abstract translation: 电路装置包括第一发光二极管和第二发光二极管，发射彼此相邻布置的不同颜色的光用于加色混合。 第一和第二可控电流源分别连接到第一和第二发光二极管，使得发光二极管的负载电流取决于由电流源接收的各个控制信号。 第一和第二Σ-Δ调制器分别连接到第一和第二发光二极管，并且提供位流作为当前源的控制信号。 每个比特流的平均值对应于相应的Σ-Δ调制器的输入信号的值。

公开(公告)号：US07012410B2

公开(公告)日：2006-03-14

申请号：US10948112

申请日：2004-09-23

Applicant: Emanuele Bodano ,  Giorgio Chiozzi ,  Andrea Logiudice ,  Salvatore Piccolella

Inventor： Emanuele Bodano ,  Giorgio Chiozzi ,  Andrea Logiudice ,  Salvatore Piccolella

IPC: G05F1/618

CPC classification number: G05F1/575

Abstract: A regulating system comprises an input terminal for applying an input voltage, and an output terminal for providing an output voltage. A semiconductor element is connected between the input terminal and the output terminal and is operable to regulate the output voltage. A regulating signal generation circuit generates the regulating signal and comprises a current mirror arrangement including a first and second current mirror path, wherein a controlled current source is connected in series to the first current mirror path. The controlled current source induces a first current dependent on one of the output signals in the first current mirror path. A second current through the second current mirror path is dependent on the first current. A splitter circuit conducts the second current to the output terminal or to a reference potential, dependent on a load path voltage applied over the load path of the semiconductor element.

Abstract translation: 调节系统包括用于施加输入电压的输入端子和用于提供输出电压的输出端子。 半导体元件连接在输入端子和输出端子之间，并且可操作以调节输出电压。 调节信号产生电路产生调节信号，并且包括包括第一和第二电流镜路径的电流镜装置，其中受控电流源与第一电流镜路径串联连接。 受控电流源引起取决于第一电流镜像路径中的一个输出信号的第一电流。 通过第二电流镜像路径的第二电流取决于第一电流。 取决于施加在半导体元件的负载路径上的负载路径电压，分路器电路将第二电流传导到输出端或参考电位。

公开(公告)号：US20050099169A1

公开(公告)日：2005-05-12

申请号：US10948112

申请日：2004-09-23

Applicant: Emanuele Bodano ,  Giorgio Chiozzi ,  Andrea Logiudice ,  Salvatore Piccolella

Inventor： Emanuele Bodano ,  Giorgio Chiozzi ,  Andrea Logiudice ,  Salvatore Piccolella

IPC: G05F1/575 ,  H03F3/04

CPC classification number: G05F1/575

Abstract: A regulating system comprising: an input terminal (K10) for applying an input voltage (Vin), an output terminal (K20) for providing an output voltage (Vout) and an output current (Iout), a semiconductor element (Q1) regulating the output voltage (Vout), which element has a load path which is connected between the input terminal (K1) and the output terminal (K2), and a control input to which a regulating signal (Ib1) is applied, a regulating signal generation circuit to generate the regulating signal (Ib1), which circuit has a current mirror arrangement (Q2, Q3) including a first and second current mirror path, wherein a controlled current source (Q4) is connected in series to the first current mirror path, which source induces a first current dependent on one of the output signals (Vout) in the first current mirror path, and wherein a second current (I2) through the second current mirror path is dependent on the first current (I1), a splitter circuit (20) which conducts the second current (I2) to the output terminal (K2) or to a reference potential (GND), dependent on a load path voltage (Vec1) applied over the load path of the semiconductor element (Q1).

Abstract translation: 一种调节系统，包括：用于施加输入电压（Vin）的输入端子（K 10），用于提供输出电压（Vout）和输出电流（Iout）的输出端子（K 20），半导体元件 ）调节输出电压（Vout），该元件具有连接在输入端子（K 1）和输出端子（K 2）之间的负载路径以及施加调节信号（Ib 1）的控制输入端 ，用于产生调节信号（Ib 1）的调节信号发生电路，该电路具有包括第一和第二电流镜通路的电流镜布置（Q 2，Q 3），其中控制电流源（Q 4）被连接 与第一电流镜像路径串联，该源引起取决于第一电流镜像路径中的一个输出信号（Vout）的第一电流，并且其中通过第二电流镜像路径的第二电流（I 2）取决于 第一电流（I 1），分离器电路（20） h根据施加在半导体元件（Q1）的负载路径上的负载路径电压（Vec 1），将第二电流（I 2）传导到输出端子（K 2）或参考电位（GND）。

公开(公告)号：US06194761B1

公开(公告)日：2001-02-27

申请号：US09232336

申请日：1999-01-15

Applicant: Giorgio Chiozzi ,  Antonio Andreini

Inventor： Giorgio Chiozzi ,  Antonio Andreini

IPC: H01L2976

CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract translation: n沟道VDMOS晶体管形成在具有结隔离的集成电路的n型有源区中。 为了防止可能损坏或破坏栅极电介质的源极和栅极之间的过电压，p沟道MOS晶体管形成在相同的有源区中，并且其栅电极连接到VDMOS晶体管的栅极电极，其源极区域 与VDMOS晶体管的源极区共用，并且其漏极区域连接到p型结隔离区域。 p沟道MOS晶体管具有低于VDMOS晶体管的栅极电介质的击穿电压的阈值电压，使其作为电压限制器。

公开(公告)号：US5917382A

公开(公告)日：1999-06-29

申请号：US739328

申请日：1996-10-30

Applicant: Giorgio Chiozzi

Inventor： Giorgio Chiozzi

IPC: H03F1/52

CPC classification number: H03F1/523

Abstract: A sensor of instantaneous power which is dissipated through a power transistor of the MOS type connected between the output terminal of a power stage and ground. It comprises a MOS transistor having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node which is coupled to the output terminal by means of a current mirror circuit which includes a resistive element in its input leg. Connected to the circuit node is the base terminal of a bipolar transistor which is respectively connected, through a diode and a constant current generator between the output terminal and ground.

Abstract translation: 瞬时功率传感器，通过连接在功率级的输出端子和地之间的MOS型功率晶体管而消耗。 它包括MOS晶体管，其栅极端子连接到功率晶体管的栅极端子，源极端子连接到地，而漏极端子连接到电路节点，该电路节点通过电流镜电路耦合到输出端子，电流镜电路包括电阻元件 在其输入腿。 连接到电路节点的是双极晶体管的基极端子，分别通过二极管和输出端子和地之间的恒流发生器连接。

公开(公告)号：US20120194164A1

公开(公告)日：2012-08-02

申请号：US13017659

申请日：2011-01-31

Applicant: Andrea Logiudice ,  Giorgio Chiozzi

Inventor： Andrea Logiudice ,  Giorgio Chiozzi

IPC: G05F3/02 ,  G01R19/00

CPC classification number: H02M3/156 ,  H02M3/005 ,  H02M3/155 ,  H02M3/157 ,  H02M2001/0009

Abstract: Disclosed is a Ćuk based current source, a control circuit for a Ćuk based current source, and a method for providing a current.

Abstract translation: 公开了一种基于Ćuk的电流源，用于基于Ćuk的电流源的控制电路以及用于提供电流的方法。

公开(公告)号：US20090134489A1

公开(公告)日：2009-05-28

申请号：US11944720

申请日：2007-11-26

Applicant: Giorgio Chiozzi

Inventor： Giorgio Chiozzi

IPC: H01L23/02 ,  H01Q1/00

CPC classification number: H01Q1/2283 ,  H01L23/645 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/19104 ,  H01Q1/007 ,  H01Q7/00 ,  H01L2924/00

Abstract: A system including an inter-chip communication system is disclosed. One embodiment includes a base chip including a base chip transceiver network. At least one chip is stacked on the base chip, the at least one stacked chip including a substrate, a cavity formed in the substrate, a first surface, and a stacked chip transceiver network disposed on the first surface adjacent to the cavity.

Abstract translation: 公开了一种包括芯片间通信系统的系统。 一个实施例包括包括基本芯片收发器网络的基本芯片。 至少一个芯片堆叠在基底芯片上，至少一个堆叠的芯片包括衬底，形成在衬底中的空腔，第一表面和布置在与空腔相邻的第一表面上的堆叠芯片收发器网络。

公开(公告)号：US06175478B1

公开(公告)日：2001-01-16

申请号：US09307082

申请日：1999-05-07

Applicant: Giorgio Chiozzi ,  Bruno Marcone

Inventor： Giorgio Chiozzi ,  Bruno Marcone

IPC: H02H300

CPC classification number: H03F1/523

Abstract: A short-circuit protection circuit, particularly for power transistors, contains a first circuit for mirroring the output current of a power transistor which is parallel-connected to the power transistor, and a second mirroring circuit which is series-connected to the first mirroring means and is adapted to emit a current which is correlated to the current mirrored by the first mirroring circuit, for comparison with a reference current. The result of the comparison determines the need to intervene or not on the power transistor. The short-circuit protection circuit may also contain a circuit for sensing the voltage drop across the power transistor which is parallel-connected to the power transistor and to the first mirroring circuit, in order to adjust minimum and maximum values of the current in output from the power transistor, as a function of the voltage that is present across the transistor.

Abstract translation: 特别是用于功率晶体管的短路保护电路包含用于镜像并联连接到功率晶体管的功率晶体管的输出电流的第一电路和与第一反射装置串联连接的第二反射电路 并且适于发射与由第一镜像电路镜像的电流相关的电流，以便与参考电流进行比较。 比较的结果决定了在功率晶体管上干涉的需要。 短路保护电路还可以包含用于感测并联连接到功率晶体管和第一反射电路的功率晶体管两端的电压降的电路，以便调整从第一反射电路的输出中的电流的最小值和最大值 功率晶体管作为晶体管两端存在的电压的函数。

公开(公告)号：US6137364A

公开(公告)日：2000-10-24

申请号：US236800

申请日：1999-01-25

Applicant: Giorgio Chiozzi

Inventor： Giorgio Chiozzi

IPC: H03F3/30 ,  H03F3/45

CPC classification number: H03F3/3093

Abstract: An integrated amplifier includes a differential input stage including a first pair of bipolar junction transistors. A reference bias current generator biases the differential input stage with a reference bias current. A first and a second current mirror circuit drives a respective transistor of the first pair of bipolar junction transistors. Each of the first and second current mirror circuits includes a transistor having a base terminal connected to an intermediate node. An integrated resistor is connected to the intermediate node and is in series with the respective transistor of the first pair of bipolar junction transistors. The reference bias current of the differential input stage conducts through the integrated resistor. The reference bias current corresponds to a ratio between a base emitter junction voltage and a resistance of the integrated resistor. An output stage includes a second pair of bipolar junction transistors, which are controlled by a respective transistor of the first and second current mirror circuits.

Abstract translation: 集成放大器包括具有第一对双极结型晶体管的差分输入级。 参考偏置电流发生器用参考偏置电流偏置差分输入级。 第一和第二电流镜电路驱动第一对双极结型晶体管的相应晶体管。 第一和第二电流镜电路中的每一个包括具有连接到中间节点的基极端子的晶体管。 集成电阻器连接到中间节点并与第一对双极结型晶体管的相应晶体管串联。 差分输入级的参考偏置电流通过集成电阻进行导通。 参考偏置电流对应于基极发射极结电压和集成电阻的电阻之间的比值。 输出级包括由第一和第二电流镜电路的相应晶体管控制的第二对双极结型晶体管。

公开(公告)号：US5663681A

公开(公告)日：1997-09-02

申请号：US423565

申请日：1995-04-14

Applicant: Edoardo Botti ,  Giorgio Chiozzi

Inventor： Edoardo Botti ,  Giorgio Chiozzi

IPC: H03F1/30 ,  H03F3/181 ,  H03F3/72 ,  H03G3/34 ,  H03F1/26

CPC classification number: H03G3/348 ,  H03F1/305 ,  H03F3/72

Abstract: A low frequency amplifier comprising, in series, a first input stage, an intermediate amplifying stage and a final stage. The intermediate amplifying stage comprises a capacitor which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier during the transient interval between the disabled and operating condition of the amplifier, a second input stage is provided which is only turned on during the transient interval, and is connected to the capacitor to detect its voltage and charge it. During the transient interval, the final stage is disabled. Upon the capacitor reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage and the final stage are enabled to turn on the amplifier.

Abstract translation: 一种低频放大器，其包括串联的第一输入级，中间放大级和最后级。 中间放大级包括当放大器禁用时放电的电容器，并且当放大器工作时被充电到预定的偏置值。 为了防止在放大器的禁用和运行状态之间的瞬态间隔期间放大器输出端的电压峰值，提供了仅在瞬变间隔期间导通的第二输入级，并连接到电容器以检测其电压 并收取费用。 在瞬态间隔期间，最后一级被禁用。 当电容器达到预定电荷值时，第二输入级实际上自动关闭，然后禁用; 并且同时第一输入级和最后级都能够使放大器导通。