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1.发明授权公开(公告)号：US06194761B1
公开(公告)日：2001-02-27
申请号：US09232336
申请日：1999-01-15
申请人： Giorgio Chiozzi , Antonio Andreini
发明人： Giorgio Chiozzi , Antonio Andreini
IPC分类号： H01L2976
CPC分类号： H01L27/0251 , H01L29/0619 , H01L29/7809 , H01L29/7811
摘要： The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.
摘要翻译： n沟道VDMOS晶体管形成在具有结隔离的集成电路的n型有源区中。 为了防止可能损坏或破坏栅极电介质的源极和栅极之间的过电压，p沟道MOS晶体管形成在相同的有源区中，并且其栅电极连接到VDMOS晶体管的栅极电极，其源极区域 与VDMOS晶体管的源极区共用，并且其漏极区域连接到p型结隔离区域。 p沟道MOS晶体管具有低于VDMOS晶体管的栅极电介质的击穿电压的阈值电压，使其作为电压限制器。
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公开(公告)号：US20050035468A1
公开(公告)日：2005-02-17
申请号：US10864901
申请日：2004-06-09
IPC分类号： H01L23/485 , H01L23/48
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译： 描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述 信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。
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3.发明授权
公开(公告)号：US5602914A
公开(公告)日：1997-02-11
申请号：US509773
申请日：1995-08-01
摘要： Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.
摘要翻译： 用于限制电话机械开关的工作电压的装置包括用于连接到电话线的端子，用于从第一端子延伸的控制电路的连接和电源分支，该分支具有第一开关，第一齐纳二极管的阴极端子 二极管和第一MOSFET晶体管的源极端子连接到第一开关的输出端子，第一MOSFET晶体管的栅极端子通过齐纳二极管的阳极端子连接到第一端子。 可以调节由装置吸收的电流。
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公开(公告)号：US07126230B2
公开(公告)日：2006-10-24
申请号：US10864901
申请日：2004-06-09
IPC分类号： H01L29/40
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译： 描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述 信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。
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5.发明授权公开(公告)号：US06362036B1
公开(公告)日：2002-03-26
申请号：US09756886
申请日：2001-01-09
申请人： Giorgio Chiozzi , Antonio Andreini
发明人： Giorgio Chiozzi , Antonio Andreini
IPC分类号： H01L218238
CPC分类号： H01L27/0251 , H01L29/0619 , H01L29/7809 , H01L29/7811
摘要： The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.
摘要翻译： n沟道VDMOS晶体管形成在具有结隔离的集成电路的n型有源区中。 为了防止可能损坏或破坏栅极电介质的源极和栅极之间的过电压，p沟道MOS晶体管形成在相同的有源区中，并且其栅电极连接到VDMOS晶体管的栅极电极，其源极区域 与VDMOS晶体管的源极区共用，并且其漏极区域连接到p型结隔离区域。 p沟道MOS晶体管具有低于VDMOS晶体管的栅极电介质的击穿电压的阈值电压，使其作为电压限制器。
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公开(公告)号：US4774198A
公开(公告)日：1988-09-27
申请号：US19785
申请日：1987-02-26
IPC分类号： H01L29/78 , H01L21/033 , H01L21/336 , H01L29/10 , H01L21/425
CPC分类号： H01L29/66719 , H01L21/0337 , H01L29/1095 , H01L29/66712
摘要： An improved fabrication process for vertical DMOS cells contemplates the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, also allowing the forming the source region. Opening of the relative contact is also effected by a self alignment technique, further simplifying the process.
摘要翻译： 用于垂直DMOS单元的改进的制造工艺考虑了通过放置多晶硅栅电极并利用栅电极本身作为用于植入和扩散体区的掩模的先前定义的栅极区域，同时使用自身进行形成短区域 对准技术，其允许容易地控制区域本身的横向延伸。 非临界掩模定义了在源极电极和DMOS电池中间的源极和体区之间的短路接触将被制成的区域，也允许形成源极区域。 相对接触的打开也通过自对准技术进行，进一步简化了过程。
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7.发明授权Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground 失效薄的外延复原集成电路，包含高压p沟道和n沟道器件，源极或漏极不接地
公开(公告)号：US5852314A
公开(公告)日：1998-12-22
申请号：US643152
申请日：1996-04-30
IPC分类号： H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/0878 , H01L27/0623 , H01L27/0922 , H01L29/1083 , H01L29/7816 , H01L29/7835 , H01L29/0615 , H01L29/0619 , H01L29/42368
摘要： N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.
摘要翻译： 集成在BiCMOS集成电路中并利用RESURF条件的用于高电压的N沟道LDMOS和p沟道MOS器件具有与外延层相同类型的导电性的掩埋区域和掺杂水平之间的掺杂水平 外延层和阱区的掺杂水平。 这些器件可能被配置为源或漏源从器件而没有问题。
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8.发明授权
公开(公告)号：US5448636A
公开(公告)日：1995-09-05
申请号：US017789
申请日：1993-02-16
摘要： Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.
摘要翻译： 用于限制电话机械开关的工作电压的装置包括用于连接到电话线的端子，用于从第一端子延伸的控制电路的连接和电源分支，该分支具有第一开关，第一齐纳二极管的阴极端子 二极管和第一MOSFET晶体管的源极端子连接到第一开关的输出端子，第一MOSFET晶体管的栅极端子通过齐纳二极管的阳极端子连接到第一端子。 可以调节由装置吸收的电流。
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9.发明授权Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices 失效包括CMOS和高压电子器件的半导体集成电路的制造方法
公开(公告)号：US4892836A
公开(公告)日：1990-01-09
申请号：US028842
申请日：1987-03-23
IPC分类号： H01L21/033 , H01L21/76 , H01L21/8234 , H01L21/8236 , H01L21/8238 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L21/8236 , H01L21/033 , H01L21/823456 , H01L27/0922
摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.
摘要翻译： 该方法需要减少数量的工艺阶段并提供有效的高电压结构，包括通过硼原子注入通过保护掩模形成CMOS器件的N沟道晶体管的P阱区域，形成 围绕所述CMOS器件的至少一个绝缘区域，形成具有与所述绝缘区域相同的导电类型但在所述绝缘区域的至少一部分上以及所述高压电子器件中的较小的杂质浓度的边缘区域，借助于所述绝缘区域 用于形成P阱区的相同的硼原子注入。
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10.发明授权Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopants 失效制造包含P沟道MOS晶体管的集成电路和利用硼和砷作为掺杂剂的双极晶体管
公开(公告)号：US4721686A
公开(公告)日：1988-01-26
申请号：US6037
申请日：1987-01-22
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L21/8222 , H01L21/8234 , H01L21/8236 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/78 , H01L21/38 , H01L21/425
CPC分类号： H01L21/8249 , H01L21/22 , H01L21/2253 , H01L21/2652 , H01L21/8234 , H01L21/8236 , H01L21/8238
摘要： This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.
摘要翻译： 相对于已知方法需要较少数量的掩模步骤的该方法包括通过适当的掩模在外延层的表面上的硼注入而不进行掩模，并且在外延层表面的预定位置进行砷注入。 然后随后的热处理导致注入的砷和硼原子的扩散，但是通过与后者的相互作用来防止在其中也发生砷注入的区域中的硼扩散，从而获得具有N +型导电性的区域，其中两个硼 已经植入了砷，并且仅植入硼的P型导电性区域。
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