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公开(公告)号：US20090278603A1
公开(公告)日：2009-11-12
申请号：US11577308
申请日：2005-10-13
CPC分类号： G05F3/262
摘要： The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T4, QO, T1) interposed between a positive supply plane (VCC) and an input node (104, 202, 310) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node (104, 202, 310). An output n-type transistor (T3, Q1, T2) is interposed between the positive supply plane (VCC) and an output node (106, 204, 314) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node (106, 204, 314). A feedback circuit equals base-emitter voltages of the input (T4, QO, T1) and the output transistor (T3, Q1, T2) in order to mirror the emitter current of the input transistor (T4, QO, T1) to the emitter current of the output transistor (T3, Q1, T2). The all n-type transistor current mirror is highly advantageous by overcoming the shortcomings of technologies such as MOBI3, GaAs, and InP of being unable to provide p-type transistors.
摘要翻译： 本发明涉及用于将输入电流镜像到输出电流的全n型晶体管电流镜。 电流镜包括插入正电源平面（VCC）和输入节点（104,202,310）之间的输入n型晶体管（T4，QO，T1），其集电极连接到正电源平面（VCC） 并且其发射极连接到输入节点（104,202,310）。 输出n型晶体管（T3，Q1，T2）介于正电源平面（VCC）和输出节点（106,204,314）之间，其集电极连接到正电源平面（VCC）及其发射极 连接到输出节点（106,204,314）。 反馈电路等于输入（T4，QO，T1）和输出晶体管（T3，Q1，T2）的基极 - 发射极电压，以便将输入晶体管（T4，QO，T1）的发射极电流镜像到发射极 输出晶体管（T3，Q1，T2）的电流。 所有n型晶体管电流镜通过克服诸如MOBI3，GaAs和InP等不能提供p型晶体管的技术的缺点是非常有利的。
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公开(公告)号：US20120105128A1
公开(公告)日：2012-05-03
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： G06G7/12
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译： 一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。 无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。 每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。 校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4） 的加权模块以使输出信号匹配期望的输出信号。
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公开(公告)号：US09413407B2
公开(公告)日：2016-08-09
申请号：US13178559
申请日：2011-07-08
申请人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
发明人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
摘要： The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
摘要翻译： 本发明涉及频率转换系统，特别是用作射频（RF）接收机或发射机中的上转换器或下变频器，包括射频信号输入的射频接收机的示例性实施例; 混合模块，其包括经由开关连接到RF信号输入的第一多个IF放大器; 配置为向每个开关提供切换信号的多相本地振荡器信号发生器; 以及求和模块，被配置为从每个IF放大器接收输出信号，并且从IF放大器输出信号的加权和提供第二多个输出IF信号，其中第二多个不同于第一多个。
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公开(公告)号：US08378720B2
公开(公告)日：2013-02-19
申请号：US13002818
申请日：2009-07-07
IPC分类号： H03B19/00
CPC分类号： H03K23/54
摘要： A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.
摘要翻译： 信号处理装置包括被布置为具有数据输入的时钟延迟线（CDL）的一系列锁存器（XDL，L1，L2）和彼此耦合以形成反相环路的数据输出。 使能电路（ACDL）允许或防止一系列锁存器中的锁存器（L2）根据一个时钟周期之前的锁存器是否分别接收到给定的二进制值或者给定的二进制值5的反相来改变状态 ，从一系列闩锁中的先前锁存（L1）开始。 这种电路配置允许以相对小的占空比误差的低成本分频奇数。
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5.发明授权Device for receiving a RF signal with loop-through output and method for looping a RF input signal through a device for receiving RF signals 有权用于接收具有环通输出的RF信号的装置以及用于通过用于接收RF信号的装置对RF输入信号进行环路的方法公开(公告)号：US08207878B2
公开(公告)日：2012-06-26
申请号：US12744693
申请日：2008-11-24
IPC分类号： H03M1/10
摘要： A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).
摘要翻译： 提供了一种用于接收具有环通输出（16）的RF信号（1; 21）的装置。 该装置包括：接收RF输入信号的输入端（3）; 将所述RF输入信号（2）转换为数字信号（9）的模拟数字转换器（8）; 数字信号处理单元（10）数字处理数字信号（9）; 将经处理的数字信号（13）转换成对应于RF输入信号（2）的环通RF信号（15）的数模转换器（14）; 以及输出环通RF信号（15）的环路输出（16）。
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公开(公告)号：US20120008717A1
公开(公告)日：2012-01-12
申请号：US13178559
申请日：2011-07-08
申请人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
发明人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
摘要： The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver (1000) comprising: an RF signal input (1001); a mixing module (1002) comprising a first plurality of IF amplifiers (10041-3) each connected to the RF signal input (1001) via a switch (10031-3); a multi-phase local oscillator signal generator (1300) configured to provide a switching signal to each switch (10031-3); and a summing module (1005) configured to receive output signals from each of the IF amplifiers (10041-3) and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
摘要翻译： 本发明涉及频率转换系统，特别是用作射频（RF）接收机或发射机中的上转换器或下变频器，包括射频接收机（1000）的示例性实施例包括：RF信号输入（1001）; 混合模块（1002），包括经由开关（10031-3）连接到RF信号输入（1001）的第一多个IF放大器（10041-3）; 配置为向每个开关（10031-3）提供切换信号的多相本地振荡器信号发生器（1300）; 以及被配置为从每个IF放大器（10041-3）接收输出信号并从IF放大器输出信号的加权和提供第二多个输出IF信号的求和模块（1005），其中第二多个不同 到第一个多个。
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公开(公告)号：US20110291732A1
公开(公告)日：2011-12-01
申请号：US13116967
申请日：2011-05-26
IPC分类号： G06F1/04
CPC分类号： G06F1/025
摘要： The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
摘要翻译： 本发明涉及用于提供用于数模转换器和谐波抑制混频器的本地振荡器信号的一个或多个相位的数字信号发生器。 所公开的实施例包括用于射频接收机的混频器的本地振荡器信号发生器（200），所述信号发生器（200）包括具有多个并行输出线（203）的位序发生器（201），数字信号发生器 ）和连接到位序发生器（201）的相应输出线（203）的多条输入线和时钟信号输入线（205），其中数字信号发生器（202）是 被配置为以由在时钟信号输入线（205）上提供的时钟信号给出的速率和由位序列发生器（201）的位序列给出的序列在串行输出线（204）上提供输出比特序列， 在多个输入线（203）上。
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公开(公告)号：US07313060B2
公开(公告)日：2007-12-25
申请号：US10523386
申请日：2003-07-21
IPC分类号： G11B7/00
CPC分类号： G11B20/10027 , G11B7/005 , G11B20/10009 , G11B2020/1288 , G11B2220/2541
摘要： An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.
摘要翻译： 光盘系统包括与可变增益放大器，限幅器和发生器连接的至少一个光电检测器，该可变增益放大器，限幅器和发生器处于限幅器和放大器之间的反馈路径中。 差分延时检测器提供光盘系统的输出。 发生器被配置为非线性地控制放大器，使得取决于输入信号的电平的放大器的控制环路的时间常数被补偿，并且放大器的控制环路的定时特性具有更连续的特性。 电容器形成积分器的一部分，用于使限幅器的输出电压信号的平均值等于零。
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9.发明授权Arrangement for calibrating the quiescent operating point of a push-pull amplifier 有权用于校准推挽放大器的静态工作点的布置公开(公告)号：US08354886B2
公开(公告)日：2013-01-15
申请号：US13058276
申请日：2009-08-10
IPC分类号： H03F3/26
CPC分类号： H03F1/308 , H03F1/3217 , H03F3/3028 , H03F3/345 , H03F2203/30003 , H03F2203/30033
摘要： A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, −). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
摘要翻译： 信号处理装置包括放大器（AMP V1），放大器（AMP V1）包括具有串联布置在两条电源线（+， - ）之间的相反导电类型的互补晶体管（MP3，MN3）的平台。 提供了可控偏置电路（CCS），用于根据控制信号（CS）来改变级的静态工作点。 控制装置测量放大器（AMP V1）的偶数阶失真5并调整控制信号（CS），使偶数阶失真低于临界水平。
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公开(公告)号：US08135375B2
公开(公告)日：2012-03-13
申请号：US12065315
申请日：2006-08-23
IPC分类号： H04B1/16
CPC分类号： H03G3/3052
摘要： A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).
摘要翻译： 增益可控级（CLN，A1，A2 ...，A7，ACC）包括一个无功信号分频器（CLN），后面是一个放大器装置（A1，A2 ... A7，ACC）。 无功信号分配器（CLN）可以是例如电容梯形网络的形式。 增益可控级（CLN，A1，A2 ... A7，ACC）具有取决于无功信号分频器（CLN）提供的信号分配因子的增益因子。 无功信号分频器（CLN）形成滤波器（LC）的一部分。 基于接收机调谐的频率（F）和信号强度指示（RS）来调整信号分配因子。
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