公开(公告)号：US20220199810A1

公开(公告)日：2022-06-23

申请号：US17130121

申请日：2020-12-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Ali Razavieh ,  Haiting Wang

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

公开(公告)号：US11094794B2

公开(公告)日：2021-08-17

申请号：US16585671

申请日：2019-09-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ali Razavieh ,  Haiting Wang

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L21/764 ,  H01L21/768 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts.

公开(公告)号：US20210233999A1

公开(公告)日：2021-07-29

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11049934B2

公开(公告)日：2021-06-29

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786 ,  H01L21/321 ,  H01L21/3105

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

公开(公告)号：US20210118993A1

公开(公告)日：2021-04-22

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US11362177B2

公开(公告)日：2022-06-14

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11205699B2

公开(公告)日：2021-12-21

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US20230061156A1

公开(公告)日：2023-03-02

申请号：US17687741

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ali Razavieh ,  Jagar Singh ,  Haiting Wang

IPC: H01L29/735 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/73

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

公开(公告)号：US12170315B2

公开(公告)日：2024-12-17

申请号：US17569897

申请日：2022-01-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Haiting Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.

公开(公告)号：US11967637B2

公开(公告)日：2024-04-23

申请号：US17687741

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ali Razavieh ,  Jagar Singh ,  Haiting Wang

IPC: H01L29/735 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/7302 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/737 ,  H01L29/785

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.