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    Hybrid optical and EUV lithography
    1.
    发明授权
    Hybrid optical and EUV lithography 有权

    公开(公告)号：US11061315B2

    公开(公告)日：2021-07-13

    申请号：US16191589

    申请日：2018-11-15

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jia Zeng ,  Guillaume Bouche ,  Lei Sun ,  Geng Han

    IPC: H01L21/00 ,  G03F1/24 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/308

    Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    2.
    发明公开
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 审中-公开

    公开(公告)号：US20230395502A1

    公开(公告)日：2023-12-07

    申请号：US18362044

    申请日：2023-07-31

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/53295 ,  H01L21/76879 ,  H01L21/02164

    Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    3.
    发明申请
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 有权

    公开(公告)号：US20220108950A1

    公开(公告)日：2022-04-07

    申请号：US17553924

    申请日：2021-12-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

    Metallization lines on integrated circuit products
    7.
    发明授权
    Metallization lines on integrated circuit products 有权

    公开(公告)号：US11233006B2

    公开(公告)日：2022-01-25

    申请号：US16103372

    申请日：2018-08-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

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