公开(公告)号：US20230124962A1

公开(公告)日：2023-04-20

申请号：US17503345

申请日：2021-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： VIBHOR JAIN ,  JOHNATAN AVRAHAM KANTAROVSKY ,  MARK DAVID LEVY ,  EPHREM GEBRESELASIE ,  YVES NGU ,  SIVA P. ADUSUMILLI

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240222224A1

公开(公告)日：2024-07-04

申请号：US18148404

申请日：2022-12-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： SIVA P. ADUSUMILLI ,  STEVEN SHANK ,  RAJENDRAN KRISHNASAMY ,  YVES NGU

IPC: H01L23/46 ,  H01L21/20 ,  H01L21/768 ,  H01L23/13

CPC classification number: H01L23/46 ,  H01L21/20 ,  H01L21/76882 ,  H01L23/13

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel, and a semiconductor device. The channel is in the substrate for a fluid to flow through and includes a first channel portion having a first volume, a second channel portion having a second volume, and a third channel portion connecting the first channel portion to the second channel portion. The third channel portion has a third volume smaller than the first volume and the second volume. The semiconductor device is vertically over the channel.

公开(公告)号：US20220165853A1

公开(公告)日：2022-05-26

申请号：US17650854

申请日：2022-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： JOHNATAN AVRAHAM KANTAROVSKY ,  RAJENDRAN KRISHNASAMY ,  SIVA P. ADUSUMILLI ,  STEVEN BENTLEY ,  MICHAEL JOSEPH ZIERAK ,  JEONGHYUN HWANG

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

公开(公告)号：US20240038882A1

公开(公告)日：2024-02-01

申请号：US18487115

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： VIBHOR JAIN ,  JOHNATAN AVRAHAM KANTAROVSKY ,  MARK DAVID LEVY ,  EPHREM GEBRESELASIE ,  YVES NGU ,  SIVA P. ADUSUMILLI

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/66431 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/435

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240038881A1

公开(公告)日：2024-02-01

申请号：US18487114

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： VIBHOR JAIN ,  JOHNATAN AVRAHAM KANTAROVSKY ,  MARK DAVID LEVY ,  EPHREM GEBRESELASIE ,  YVES NGU ,  SIVA P. ADUSUMILLI

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/66431 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/435

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20220238409A1

公开(公告)日：2022-07-28

申请号：US17156634

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： RAMSEY HAZBUN ,  SIVA P. ADUSUMILLI ,  MARK DAVID LEVY ,  ALVIN JOSEPH

IPC: H01L23/367 ,  H01L21/48

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.