公开(公告)号：US20150228648A1

公开(公告)日：2015-08-13

申请号：US14175827

申请日：2014-02-07

Applicant: Globalfoundries Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US20190326436A1

公开(公告)日：2019-10-24

申请号：US16433626

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/161 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US20160211375A1

公开(公告)日：2016-07-21

申请号：US15082103

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US20140319614A1

公开(公告)日：2014-10-30

申请号：US13870854

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Abhijeet PAUL ,  Abner BELLO ,  Vimal K. KAMINENI ,  Derya DENIZ

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。