公开(公告)号：US06232665B1

公开(公告)日：2001-05-15

申请号：US09328117

申请日：1999-06-08

申请人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

发明人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating metal plugs, such as aluminum plugs, in a semiconductor workpiece. The invention is suitable for filling narrow, high aspect ratio holes, and the invention minimizes the formation of TiAl3 or other products of interdiffusion between the plug and the wetting layer. First, an optional barrier layer is created by covering the bottom of a hole with a film containing titanium nitride doped with silicon. Second, a wetting layer is created by covering the side walls of a hole with a film containing titanium doped with silicon, in a Ti:Si molar ratio greater than 1:2. Preferably, the wetting layer is created by sputter deposition using a titanium sputtering target containing 0.1% to 20% wt silicon, most preferably 5% to 10% wt silicon. Third, the hole is filled by depositing a material consisting primarily of aluminum. The hole preferably is filled by sputter deposition using an aluminum sputtering target, optionally containing dopants such as copper. To facilitate filling the hole without voids, the aluminum sputter deposition preferably is performed “warm”, i.e., with the workpiece at a temperature below the melting point of aluminum but high enough to promote reflow of the deposited material. The silicon atoms in the wetting layer inhibit the titanium from reacting with the aluminum, and the wetting layer facilitates filling the hole with the aluminum material without leaving unfilled voids.

摘要翻译： 一种用于在半导体工件中制造诸如铝塞的金属插头的工艺。 本发明适用于填充狭窄的高纵横比孔，并且本发明使塞子和润湿层之间的TiAl 3或其他相互扩散产物的形成最小化。 首先，通过用含有掺杂硅的氮化钛的膜覆盖孔的底部来产生可选的阻挡层。 第二，通过用含有掺杂硅的钛的膜覆盖孔的侧壁，Ti：Si摩尔比大于1:2产生润湿层。 优选地，通过使用含有0.1重量％至20重量％硅，最优选5重量％至10重量％硅的钛溅射靶的溅射沉积来产生润湿层。 第三，通过沉积主要由铝构成的材料填充孔。 优选地，通过使用铝溅射靶的溅射沉积来填充孔，任选地含有诸如铜的掺杂剂。 为了方便填充孔而没有空隙，铝溅射沉积优选地进行“暖”，即工件在低于铝的熔点的温度下，但足够高以促进沉积材料的回流。 润湿层中的硅原子阻止钛与铝反应，并且润湿层有助于用铝材料填充孔而不留下未填充的空隙。

公开(公告)号：US5911113A

公开(公告)日：1999-06-08

申请号：US820512

申请日：1997-03-18

申请人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

发明人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

摘要： A process for fabricating metal plugs, such as aluminum plugs, in a semiconductor workpiece. The invention is suitable for filling narrow, high aspect ratio holes, and the invention minimizes the formation of TiAl3 or other products of interdiffusion between the plug and the wetting layer. First, an optional barrier layer is created by covering the bottom of a hole with a film containing titanium nitride doped with silicon. Second, a wetting layer is created by covering the side walls of a hole with a film containing titanium doped with silicon, in a Ti:Si molar ratio greater than 1:2. Preferably, the wetting layer is created by sputter deposition using a titanium sputtering target containing 0.1% to 20% wt silicon, most preferably 5% to 10% wt silicon. Third, the hole is filled by depositing a material consisting primarily of aluminum. The hole preferably is filled by sputter deposition using an aluminum sputtering target, optionally containing dopants such as copper. To facilitate filling the hole without voids, the aluminum sputter deposition preferably is performed "warm", i.e., with the workpiece at a temperature below the melting point of aluminum but high enough to promote reflow of the deposited material. The silicon atoms in the wetting layer inhibit the titanium from reacting with the aluminum, and the wetting layer facilitates filling the hole with the aluminum material without leaving unfilled voids.

摘要翻译： 一种用于在半导体工件中制造诸如铝塞的金属插头的工艺。 本发明适用于填充狭窄的高纵横比孔，并且本发明使塞子和润湿层之间的TiAl 3或其他相互扩散产物的形成最小化。 首先，通过用含有掺杂硅的氮化钛的膜覆盖孔的底部来产生可选的阻挡层。 第二，通过用含有掺杂硅的钛的膜覆盖孔的侧壁，Ti：Si摩尔比大于1:2产生润湿层。 优选地，通过使用含有0.1重量％至20重量％硅，最优选5重量％至10重量％硅的钛溅射靶的溅射沉积来产生润湿层。 第三，通过沉积主要由铝构成的材料填充孔。 优选地，通过使用铝溅射靶的溅射沉积来填充孔，任选地含有诸如铜的掺杂剂。 为了方便填充孔而没有空隙，铝溅射沉积优选地进行“暖”，即工件在低于铝的熔点的温度下，但足够高以促进沉积材料的回流。 润湿层中的硅原子阻止钛与铝反应，并且润湿层有助于用铝材料填充孔而不留下未填充的空隙。

公开(公告)号：US20090053888A1

公开(公告)日：2009-02-26

申请号：US12288540

申请日：2008-10-20

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

摘要： A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.

摘要翻译： 一种用覆盖的导电层或填充物沉积具有降低半导体器件互连电阻率的渗透阻挡层的方法。 通过诱导在含钽隔离层内形成α钽来实现较低的电阻率。

公开(公告)号：US20070241458A1

公开(公告)日：2007-10-18

申请号：US11809153

申请日：2007-05-30

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

IPC分类号： H01L23/48

CPC分类号： H01L21/02183 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.

摘要翻译： 用于半导体器件应用的金属/金属氮化物阻挡层。 阻挡层在通孔的高导电性很重要的接触孔中特别有用，并且较低电阻率的阻挡层提供改进的整体通孔导电性。

公开(公告)号：US20050085068A1

公开(公告)日：2005-04-21

申请号：US10981319

申请日：2004-11-03

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US20090269922A1

公开(公告)日：2009-10-29

申请号：US12459091

申请日：2009-06-25

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括通过等离子体沉积将金属种子层的第一部分以足够的晶片衬底偏压比与DC源功率沉积在晶片上，达到底部覆盖范围，同时抑制凹陷器件特征的表面的再溅射。 该方法还包括以基板RF偏压的比例将金属种子层的第二部分沉积到DC源功率，使得不会抑制再溅射。

公开(公告)号：US20050272254A1

公开(公告)日：2005-12-08

申请号：US11184404

申请日：2005-07-18

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

IPC分类号： C23C14/06 ,  C23C14/16 ,  C23C14/32 ,  H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

摘要： We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.

摘要翻译： 我们已经发现了一种提供大约约2埃至大约100埃的Ta N种子层的薄膜的方法，当钽沉积在Ta上时可用于诱导形成α钽， SUB> N 种子层。 此外，Ta N N种子层在30μΩ·cm的范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。 在该方法的一个实施方案中，TaN膜在其表面上形成Ta N N种子层。 在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

公开(公告)号：US09390970B2

公开(公告)日：2016-07-12

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768 ,  C23C14/04 ,  C23C14/16 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层 的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US20100255678A1

公开(公告)日：2010-10-07

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US20070178682A1

公开(公告)日：2007-08-02

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/20

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。