公开(公告)号：US06225178B1

公开(公告)日：2001-05-01

申请号：US07466709

申请日：1990-01-02

申请人： Gordon A. Shaw ,  Curtis H. Rahn ,  Cheisan Yue ,  Todd A. Randazzo

发明人： Gordon A. Shaw ,  Curtis H. Rahn ,  Cheisan Yue ,  Todd A. Randazzo

IPC分类号： H01L21336

CPC分类号： H01L21/76216

摘要： A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

摘要翻译： 将硅层氧化成具有辐射硬化的还原鸟喙的装置隔离场氧化物的方法。 在氧化之前使用倾斜和旋转的场注入来增加MOS晶体管的边缘区域中的掺杂浓度，以补偿氧化过程中的硼浸出。 场氧化物通过高压氧化在低温下生长，通过制造富硅氧化物膜来增加总剂量硬度。

公开(公告)号：US20080233704A1

公开(公告)日：2008-09-25

申请号：US11690379

申请日：2007-03-23

申请人： Paul S. Fechner ,  Gordon A. Shaw

发明人： Paul S. Fechner ,  Gordon A. Shaw

IPC分类号： H01L21/20

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers.

摘要翻译： 一种电阻电容器结构及其制造方法。 电阻电容器结构在微电子电路内的至少两个节点之间提供电容。 电阻电容器结构的底板包括电阻层，其又在电路内的附加节点之间提供电阻路径。 电阻器电容器结构可以形成在层间电介质层的顶部或内部。 可选地，电阻层可以用于填充位于层间电介质层之间的空腔，并因此在层间电介质层之间提供电阻路径。

公开(公告)号：US07732287B2

公开(公告)日：2010-06-08

申请号：US11415703

申请日：2006-05-02

申请人： Paul S. Fechner ,  Gordon A. Shaw ,  Eric E. Vogt

发明人： Paul S. Fechner ,  Gordon A. Shaw ,  Eric E. Vogt

IPC分类号： H01L21/336

CPC分类号： H01L29/78615 ,  H01L29/66772

摘要： A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

摘要翻译： 一种形成身体的方法。 该方法包括在SOI工艺的STI方案期间形成体系。 在STI方案中，形成第一沟槽。 第一沟槽在SOI衬底的掩埋氧化物层之前停止。 第一沟槽可以确定在至少两个FET之间共享的身体连接的高度。 也可以在第一沟槽内形成第二沟槽。 第二沟槽在SOI衬底中停止。 第二个沟槽定义了一个领带的位置和形状。 一旦定义了身体领带的位置和形状，就会在身体绑带上方沉积氧化物。 沉积的氧化物防止某些植入物进入身体束带。 通过防止这些植入物，源极和漏极注入可以与源极和漏极区域自对准，而不需要使用光致抗蚀剂掩模来屏蔽源极和漏极植入物的主体连接区域。

公开(公告)号：US5624429A

公开(公告)日：1997-04-29

申请号：US603477

申请日：1996-03-06

申请人： Andrew M. Long ,  Andrew E. Huntoon ,  Sang V. Tran ,  Lori A. Roocks ,  Patrick R. Lord ,  Gordon A. Shaw

发明人： Andrew M. Long ,  Andrew E. Huntoon ,  Sang V. Tran ,  Lori A. Roocks ,  Patrick R. Lord ,  Gordon A. Shaw

IPC分类号： A61F13/49 ,  A44B18/00 ,  A61F5/44 ,  A61F13/56 ,  A61F13/58 ,  A61F13/62 ,  A61F13/15

CPC分类号： A61F13/5622 ,  A61F13/62 ,  Y10S2/912 ,  Y10S2/913 ,  Y10S2/914 ,  Y10S2/915 ,  Y10S24/11 ,  Y10T24/2708

摘要： A distinctive article can include an elastomerically stretchable side panel having a longitudinal dimension and a lateral dimension. A member of hook material is operably connected to a first, laterally outboard edge portion of the side panel, and each member of hook material includes a hook base layer which has an appointed fastening region and an appointed grip region. The fastening region has a plurality of hook elements which are integrally formed with the base layer and extend away from a base plane of the hook base layer. The hook elements are configured to operably engage a selected, cooperating loop material. The grip region has a relatively lower density of the hook elements per unit area, as compared to the fastening region. The fastening region is interposed between the side panel and the grip region. The grip region provides a laterally terminal edge of the article.

摘要翻译： 独特的制品可以包括具有纵向尺寸和横向尺寸的弹性伸缩侧板。 钩材料的构件可操作地连接到侧板的第一横向外侧边缘部分，并且钩材料的每个构件包括钩基部层，其具有指定的紧固区域和指定的抓握区域。 紧固区域具有与基底层一体地形成并且远离钩基底层的基面延伸的多个钩元件。 钩元件构造成可操作地接合所选择的配合的环材料。 与紧固区域相比，握持区域具有相对较低的每单位面积的钩元件的密度。 紧固区域插入在侧板和握持区域之间。 把手区域提供物品的横向终端边缘。

公开(公告)号：US07183042B2

公开(公告)日：2007-02-27

申请号：US10706067

申请日：2003-11-12

申请人： Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

发明人： Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

IPC分类号： G03F7/20

CPC分类号： G11C11/16

摘要： In a process of making a magnetoresistive memory device, a mask layout is produced by use of any suitable design tool. The mask layout is laid out in grids having a central grid forming a central section and grids forming bit end sections, and the grids of the bit end sections are rectangles. A mask is made by use of the mask layout, and the mask has stepped bit ends. The mask is used to make a magnetic storage layer having tapered bit ends, to make a magnetic sense layer having tapered bit ends, and to make a non-magnetic layer having tapered bit ends. The non-magnetic layer is between the magnetic sense layer and the magnetic storage layer.

摘要翻译： 在制造磁阻存储器件的过程中，通过使用任何合适的设计工具来生产掩模布局。 掩模布局布置在具有形成中心部分的中心格栅和形成钻头末端部分的格栅的格栅中，钻头端部的格栅为矩形。 使用掩模布局制作掩模，并且掩模具有阶梯位。 该掩模用于制造具有锥形位端的磁存储层，以形成具有锥形位端的磁感应层，并制成具有锥形位端的非磁性层。 非磁性层位于磁感应层和磁性存储层之间。

公开(公告)号：US5212108A

公开(公告)日：1993-05-18

申请号：US807307

申请日：1991-12-13

申请人： Michael S. Liu ,  Gordon A. Shaw ,  Jerry Yue

发明人： Michael S. Liu ,  Gordon A. Shaw ,  Jerry Yue

IPC分类号： H01L21/02 ,  H01L21/3215 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L21/32155 ,  H01L27/1112

摘要： A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.

摘要翻译： 一种用于制造中间值高的多晶硅电阻器的方法，用作存储器单元中的交叉耦合或单个事件镦粗（SEU）电阻器。 用砷离子注入薄的多晶硅膜以产生预定的电阻率。 然后用氟离子注入薄膜以稳定晶界，从而稳定势垒高度。 降低栅极高度从运行到晶圆运行的变化允许制造可再现的SEU电阻器。

公开(公告)号：US07383626B2

公开(公告)日：2008-06-10

申请号：US11508671

申请日：2006-08-22

申请人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

发明人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

IPC分类号： G11B5/127 ,  H04R31/00

CPC分类号： G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

摘要翻译： 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

公开(公告)号：US07114240B2

公开(公告)日：2006-10-03

申请号：US10706531

申请日：2003-11-12

申请人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

发明人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

IPC分类号： G11B5/127 ,  H04R31/00

CPC分类号： G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

摘要翻译： 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。