Line end shortening reduction during etch
    1.
    发明授权
    Line end shortening reduction during etch 有权
    刻蚀期间线端缩短缩短

    公开(公告)号:US08668805B2

    公开(公告)日:2014-03-11

    申请号:US12165539

    申请日:2008-06-30

    IPC分类号: C23F1/00 H01L21/306

    摘要: A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.

    摘要翻译: 半导体器件可以通过以下方法形成:包括在蚀刻层上提供经图案化的光致抗蚀剂掩模,光致抗蚀剂掩模具有至少一个光致抗蚀剂线,其具有终止于线端的一对侧壁,将涂层置于至少一个光致抗蚀剂线 包括至少一个循环,其中每个循环包括:a)在所述光致抗蚀剂线上沉积聚合物层,其中所述一端的聚合物的量大于所述侧壁上的聚合物的量,以及b)使所述聚合物层硬化, 并通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中,其中线端缩短(LES)小于或等于1。

    Line end shortening reduction during etch
    2.
    发明授权
    Line end shortening reduction during etch 有权
    刻蚀期间线端缩短缩短

    公开(公告)号:US07491343B2

    公开(公告)日:2009-02-17

    申请号:US11621902

    申请日:2007-01-10

    IPC分类号: B44C1/22

    摘要: A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.

    摘要翻译: 提供了一种用于蚀刻蚀刻层中的特征的方法。 提供了图案化的光致抗蚀剂掩模在蚀刻层之上,光刻胶掩模具有至少一个光致抗蚀剂线,其具有在线端终止的一对侧壁。 聚合物层放置在至少一个光致抗蚀剂线之上,其中在光致抗蚀剂线的线端处的聚合物层的厚度大于光致抗蚀剂线的侧壁上的聚合物层的厚度。 通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中,其中线端缩短(LES)比小于或等于1。

    Line end shortening reduction during etch
    3.
    发明授权
    Line end shortening reduction during etch 有权
    刻蚀期间线端缩短缩短

    公开(公告)号:US07407597B2

    公开(公告)日:2008-08-05

    申请号:US11521810

    申请日:2006-09-14

    IPC分类号: B44C1/22

    摘要: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.

    摘要翻译: 提供了一种用于蚀刻蚀刻层中的特征的方法。 在蚀刻层上形成图案化的光致抗蚀剂掩模,其中至少一个光致抗蚀剂线具有一端在端部终止的一对侧壁。 在光致抗蚀剂线路上方放置涂层,其包括在光致抗蚀剂线上沉积聚合物层的至少一个循环,其中一端的聚合物的量大于侧壁上的聚合物的量,并硬化聚合物层。 通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中,其中线端缩短(LES)小于或等于1。

    Line end shortening reduction during etch

    公开(公告)号:US20080087637A1

    公开(公告)日:2008-04-17

    申请号:US11521810

    申请日:2006-09-14

    IPC分类号: C03C25/68

    摘要: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.

    LINE END SHORTENING REDUCTION DURING ETCH
    5.
    发明申请
    LINE END SHORTENING REDUCTION DURING ETCH 有权
    在ETCH期间的线端缩短

    公开(公告)号:US20080087639A1

    公开(公告)日:2008-04-17

    申请号:US11621902

    申请日:2007-01-10

    IPC分类号: C03C25/68

    摘要: A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.

    摘要翻译: 提供了一种用于蚀刻蚀刻层中的特征的方法。 提供了图案化的光致抗蚀剂掩模在蚀刻层之上,光刻胶掩模具有至少一个光致抗蚀剂线,其具有在线端终止的一对侧壁。 聚合物层放置在至少一个光致抗蚀剂线之上,其中在光致抗蚀剂线的线端处的聚合物层的厚度大于光致抗蚀剂线的侧壁上的聚合物层的厚度。 通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中,其中线端缩短(LES)比小于或等于1。

    Selective etch of films with high dielectric constant
    6.
    发明申请
    Selective etch of films with high dielectric constant 审中-公开
    具有高介电常数的薄膜的选择性蚀刻

    公开(公告)号:US20050153563A1

    公开(公告)日:2005-07-14

    申请号:US10758637

    申请日:2004-01-14

    摘要: A method for selectively etching a high dielectric constant layer over a silicon substrate is provided. The silicon substrate is placed into an etch chamber. An etchant gas is provided into the etch chamber, where the etchant gas comprises BCl3, an inert diluent, and Cl2, where the flow ratio of the inert diluent to BCl3 is between 2:1 and 1:2, and where the flow ratio of BCl3 to Cl2 is between 2:1 and 20:1. A plasma is generated from the etchant gas to selectively etch the high dielectric constant layer.

    摘要翻译: 提供了一种用于在硅衬底上选择性蚀刻高介电常数层的方法。 将硅衬底放置在蚀刻室中。 蚀刻气体被提供到蚀刻室中,其中蚀刻剂气体包括惰性稀释剂和Cl 2 Cl 2,其中惰性稀释剂与BCl的流动比 3/3之间的比例在2:1和1:2之间,并且其中BCl 3与Cl 2的流量比在2:1和20:1之间 :1。 从蚀刻剂气体产生等离子体以选择性地蚀刻高介电常数层。

    Process controls for improved wafer uniformity using integrated or standalone metrology
    7.
    发明申请
    Process controls for improved wafer uniformity using integrated or standalone metrology 有权
    使用集成或独立计量的改进晶圆均匀性的过程控制

    公开(公告)号:US20050148104A1

    公开(公告)日:2005-07-07

    申请号:US10746969

    申请日:2003-12-24

    IPC分类号: H01L21/00 H01L21/66

    摘要: A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map into a processing parameter map, and uses the processing parameter map to tailor the subsequent processing step to that specific wafer. The wafer can also be measured after the processing to compare an actual outcome with the targeted outcome, and the difference can be used to refine the transformation from a dimension map to a processing parameter map for a subsequent wafer.

    摘要翻译: 提供了一种用于测量晶片上的多个位置的方法和装置,用于控制随后的半导体处理步骤以在该晶片上实现更大的尺寸均匀性。 该方法和装置将特征的维度映射到多个位置以创建维度图,将维度图变换为处理参数图,并使用处理参数图来定制到该特定晶片的后续处理步骤。 也可以在处理之后测量晶片以将实际结果与目标结果进行比较,并且该差异可用于细化从尺寸图到后续晶片的处理参数图的变换。