公开(公告)号：USRE36663E

公开(公告)日：2000-04-18

申请号：US473812

申请日：1995-06-07

申请人： Gregory C. Smith ,  Thomas D. Bonifield

发明人： Gregory C. Smith ,  Thomas D. Bonifield

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/00 ,  H01L21/02 ,  H01L21/283 ,  H01L21/90

CPC分类号： H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

摘要翻译： 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

公开(公告)号：US5055423A

公开(公告)日：1991-10-08

申请号：US383304

申请日：1989-07-18

申请人： Gregory C. Smith ,  Thomas D. Bonifield

发明人： Gregory C. Smith ,  Thomas D. Bonifield

IPC分类号： H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

摘要翻译： 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

公开(公告)号：US07712460B2

公开(公告)日：2010-05-11

申请号：US11820486

申请日：2007-06-19

申请人： Miroslav A. Simo ,  Gregory C. Smith

发明人： Miroslav A. Simo ,  Gregory C. Smith

IPC分类号： F41B5/18

CPC分类号： F41B5/1469 ,  F41B5/1415

摘要： A release device with a follow-through or recoil motion for use with mechanically launched projectiles. A recoil motion is in a direction opposite the path of the projectile. Releasing an arrow from a bow provides correct form and follow-through motion of a user hand directly opposite to a direction of a path of the launched arrow, to improve flight accuracy. The release device includes a housing, a trigger, a keeper and a recoil assembly. This invention also relates to a method of using the release device.

摘要翻译： 具有随机或反冲运动的释放装置，用于机械发射的射弹。 反冲运动在与弹丸的路径相反的方向。 从箭头释放箭头可以提供正确的形式和用户手的直接运动，直接与发射箭头的路径方向相对，以提高飞行精度。 释放装置包括壳体，触发器，保持器和反冲组件。 本发明还涉及一种使用该释放装置的方法。

公开(公告)号：US07710396B2

公开(公告)日：2010-05-04

申请号：US11329876

申请日：2006-01-11

申请人： Gregory C. Smith ,  Thomas J. Quinn ,  James J. Leftwich

发明人： Gregory C. Smith ,  Thomas J. Quinn ,  James J. Leftwich

IPC分类号： G09G5/08

CPC分类号： H04N21/812 ,  G06F3/017 ,  G06F3/0346 ,  G06F3/0354 ,  G06F3/0481 ,  G08C2201/32 ,  G11B15/023 ,  G11B19/025 ,  H04N5/4403 ,  H04N5/44582 ,  H04N5/76 ,  H04N21/42222 ,  H04N21/47 ,  H04N2005/4432

摘要： A user interface for multimedia centers advantageously utilizes hand-held inertial-sensing user input devices to select channels and quickly navigate the dense menus of options. Extensive use of the high resolution and bandwidth of such user input devices is combined with strategies to avoid unintentional inputs and with dense and intuitive interactive graphical displays.

公开(公告)号：US06794757B1

公开(公告)日：2004-09-21

申请号：US08866456

申请日：1997-05-30

申请人： Gregory C. Smith

发明人： Gregory C. Smith

IPC分类号： H01L2348

CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/97 ,  H01L2924/00

摘要： The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

摘要翻译： 通过绝缘层的接触开口形成为具有直的侧壁部分和碗形的侧壁部分。 碗状侧壁部分靠近绝缘层的顶部，以在顶部相对于底部提供接触开口的扩大直径。 然后在接触开口中形成与下导电层电接触的导电材料。 导电材料形成具有扩大的头部的塞子，例如钉头或平的热螺丝形状。 扩大的头部保护硅和阻挡层（如果存在）在接触件内被任何随后的各向异性蚀刻腐蚀。 因此，当诸如铝的电互连层形成在接触插塞上方时，插塞充当蚀刻停止件，以防止在接触开口内蚀刻阻挡层的阻挡层。

公开(公告)号：US6158728A

公开(公告)日：2000-12-12

申请号：US452426

申请日：1999-12-01

申请人： Gregory C. Smith

发明人： Gregory C. Smith

IPC分类号： B25B5/00 ,  B25B5/10 ,  B23Q3/02

CPC分类号： B25B5/006 ,  B25B5/104 ,  B25B5/105

摘要： A workpiece holding device for a T-slotted machine table includes a locator block having a planar bottom surface, a mounting hole that intersects the bottom surface to define a center point, at least one workpiece locating surface disposed a predetermined distance from the center point, and a key protruding from the bottom surface at a second point offset a predetermined distance from the center point. The protruding portion of the key has a width substantially the same as the T-slot opening so as to slidably mount in the T-slot. A fastener extends through the mounting hole and secures the locator block to a T-nut slidably mounted in the T-slot. A clamp secured to the locator block clamps the workpiece to the locating surface of the locator block. A method of using the device is also disclosed.

摘要翻译： 一种用于T型开槽机床的工件保持装置包括：具有平坦底面的定位块，与底面相交以限定中心点的安装孔，设置在离中心点一定距离的至少一个工件定位面， 以及在距离中心点偏移预定距离的第二点处从底表面突出的键。 键的突出部分具有与T形槽开口基本相同的宽度，从而可滑动地安装在T形槽中。 紧固件延伸穿过安装孔并将定位块固定到可滑动地安装在T形槽中的T形螺母。 固定到定位块的夹具将工件夹紧到定位块的定位表面。 还公开了使用该装置的方法。

公开(公告)号：US5955770A

公开(公告)日：1999-09-21

申请号：US877911

申请日：1997-06-18

申请人： Tsiu C. Chan ,  Gregory C. Smith

发明人： Tsiu C. Chan ,  Gregory C. Smith

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/7833

摘要： A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

摘要翻译： 提供一种用于形成半导体集成电路的平面晶体管的方法和根据该集成电路形成的集成电路。 形成多个场氧化物区域，覆盖基板，电绝缘封装在电介质中的多个晶体管。 LDD区域形成在与晶体管和场氧化物区域相邻的衬底中。 掺杂的多晶硅凸起的源极和漏极区域形成为覆盖LDD区域和场氧化物区域的锥形部分并且与晶体管相邻。 这些多晶硅升高的源极和漏极区域将有助于防止任何不希望量的衬底硅被消耗，减少了结漏电和穿透的可能性，并且为随后的处理步骤提供了更平的表面。

公开(公告)号：US5682055A

公开(公告)日：1997-10-28

申请号：US480857

申请日：1995-06-07

申请人： Kuei-wu Huang ,  Tsiu C. Chan ,  Gregory C. Smith

发明人： Kuei-wu Huang ,  Tsiu C. Chan ,  Gregory C. Smith

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94 ,  H01L29/04

CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L21/762 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42316 ,  H01L29/66628 ,  H01L29/7833

摘要： A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

摘要翻译： 提供一种用于形成半导体集成电路的改进的平面结构的方法和根据该集成电路形成的集成电路。 跨越集成电路生长的场氧化物被图案化和蚀刻以形成具有基本上垂直的侧壁的开口，暴露出将形成有源区域的场氧化物下面的衬底的上表面的一部分。 在衬底的暴露部分上形成包括多晶硅栅电极和栅极氧化物的栅电极。 多晶硅栅极在场氧化物的上表面的高度处或其上方的衬底上方具有高度。 栅极优选还包括多晶硅上方的硅化物和硅化物上方的氧化物覆盖层。 LDD区域形成在与栅电极相邻的衬底中，并且沿着包括硅化物和覆盖层的栅电极的侧面形成侧壁间隔物。

公开(公告)号：US08340420B2

公开(公告)日：2012-12-25

申请号：US12573556

申请日：2009-10-05

申请人： Gregory C. Smith ,  Shana S. Smith

发明人： Gregory C. Smith ,  Shana S. Smith

IPC分类号： G06K9/00 ,  G06K9/34

CPC分类号： G06K9/4647 ,  G06K9/00818

摘要： A method for recognizing objects in images is disclosed. The method of the present invention comprises the following steps. First, acquire a digital image. Then, select one or more objects from the image according to a certain characteristic. Next, generate an x-axis histogram and/or a y-axis histogram from the segmented image. Then, find the zeroes and maxima for the x-axis histogram and/or the y-axis histogram and use the polynomial regression analysis to determine the shape, shape and location of each of the objects in the segmented image according to the zeroes and maxima. If the two curves linking two zeroes and one maximum in the x-axis histogram and the y-axis histogram are two sloped line, the corresponding object may be determined to be a triangle. If each of the four curves linking two zeroes and two maxima is a line, the corresponding object may be determined to be a rectangle.

摘要翻译： 公开了一种用于识别图像中的对象的方法。 本发明的方法包括以下步骤。 首先，获取数字图像。 然后，根据某一特性从图像中选择一个或多个对象。 接下来，从分割图像生成x轴直方图和/或y轴直方图。 然后，找到x轴直方图和/或y轴直方图的零点和最大值，并使用多项式回归分析根据零点和最大值确定分割图像中每个对象的形状，形状和位置 。 如果在x轴直方图和y轴直方图中连接两个零和一个最大值的两条曲线是两条倾斜线，则可以将相应的对象确定为三角形。 如果链接两个零和两个最大值的四个曲线中的每一个是一行，则相应的对象可以被确定为矩形。

公开(公告)号：US07855139B2

公开(公告)日：2010-12-21

申请号：US11754845

申请日：2007-05-29

申请人： Gregory C. Smith

发明人： Gregory C. Smith

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76834

摘要： Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.

摘要翻译： 显示和描述了用于控制半导体器件中使用的材料的有效介电常数的系统和方法。 在一个实施例中，一种方法包括提供半导体衬底，其上形成有多个柱，在多个柱上沉积介电材料的第一层，去除沉积在多个柱上的第一层的一部分，以及沉积第二层 电介质材料层在多个柱上，其中第二层在多个柱之间留下多个空隙。