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    Planarized selective tungsten metallization system
    1.
    再颁专利
    Planarized selective tungsten metallization system 失效
    平面选择性钨金属化系统

    公开(公告)号：USRE36663E

    公开(公告)日：2000-04-18

    申请号：US473812

    申请日：1995-06-07

    Applicant: Gregory C. Smith ,  Thomas D. Bonifield

    Inventor： Gregory C. Smith ,  Thomas D. Bonifield

    IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/00 ,  H01L21/02 ,  H01L21/283 ,  H01L21/90

    CPC classification number: H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

    Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

    Abstract translation: 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

    Planarized selective tungsten metallization system
    2.
    发明授权
    Planarized selective tungsten metallization system 失效
    平面选择性钨金属化系统

    公开(公告)号：US5055423A

    公开(公告)日：1991-10-08

    申请号：US383304

    申请日：1989-07-18

    Applicant: Gregory C. Smith ,  Thomas D. Bonifield

    Inventor： Gregory C. Smith ,  Thomas D. Bonifield

    IPC: H01L21/3205 ,  H01L21/768

    CPC classification number: H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

    Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

    Abstract translation: 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

    TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices
    9.
    发明申请
    TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices 审中-公开
    TSVS具有化学暴露的集成电路器件的TSV提示

    公开(公告)号：US20110018107A1

    公开(公告)日：2011-01-27

    申请号：US12899754

    申请日：2010-10-07

    Applicant: Thomas D. Bonifield ,  Brian E. Goodlin ,  Mona M. Eissa

    Inventor： Thomas D. Bonifield ,  Brian E. Goodlin ,  Mona M. Eissa

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

    Abstract translation: 一种用于制造IC的方法，包括从第一至第
    一通孔（TSV）和IC及其电子组件。 提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。 基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。 在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。 用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。 化学蚀刻通常是三步化学蚀刻。

    Plasma reactor with reduced chamber wall deposition
    10.
    发明授权
    Plasma reactor with reduced chamber wall deposition 失效
    具有减小室壁沉积的等离子体反应器

    公开(公告)号：US4513021A

    公开(公告)日：1985-04-23

    申请号：US549217

    申请日：1983-11-07

    Applicant: Andrew J. Purdes ,  Thomas D. Bonifield

    Inventor： Andrew J. Purdes ,  Thomas D. Bonifield

    IPC: C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  H01J37/32 ,  B05D3/06

    CPC classification number: C23C16/45508 ,  C23C16/45519 ,  C23C16/4558 ,  C23C16/5096 ,  H01J37/3244

    Abstract: A plasma reactor wherein material deposition on the sidewall is substantially prevented. In a radial flow reactor, wherein the reagent gases are injected at periphery of an annular substrate holder and exhausted near the center of the holder, a second gas flow of diluent gases is provided, which also flows radially to be exhausted at the center of the substrate holder. Since the diluent gas flow begins outboard of the reagent gas flow, the gas flow across the reagent gas injection nozzles prevents reagent gases from flowing outward. Thus, the gas adjacent to the chamber wall is almost entirely composed of the inert diluent gas, and material deposition on reactor walls is prevented.

    Abstract translation: 基本上防止了侧壁上的材料沉积的等离子体反应器。 在径向流动反应器中，其中反应物气体在环形衬底保持器的周围注入并在保持器的中心附近排出，提供稀释气体的第二气流，其也径向流动以在 基板支架 由于稀释剂气体流从反应气流的外侧开始，所以穿过反应气注入喷嘴的气流阻止反应气体向外流出。 因此，邻近室壁的气体几乎完全由惰性稀释气体组成，并且防止了反应器壁上的材料沉积。

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