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    Structure and method for hybrid tungsten copper metal contact
    1.
    发明授权
    Structure and method for hybrid tungsten copper metal contact 失效
    混合钨铜金属接触的结构和方法

    公开(公告)号：US07629264B2

    公开(公告)日：2009-12-08

    申请号：US12099996

    申请日：2008-04-09

    申请人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

    发明人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

    IPC分类号： H01L21/302

    CPC分类号： H01L23/5329 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76835 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).

    摘要翻译： 本发明在一个实施例中提供了一种形成互连的方法，包括：在衬底顶部提供层间电介质层，所述层间电介质层包括从层间电介质的上表面延伸到衬底的至少一个钨（W）柱; 将所述至少一个钨（W）螺柱的上表面凹陷在所述层间电介质的上表面下方，以提供至少一个凹入的钨（W）螺柱; 在所述层间介电层的上表面和所述至少一个凹入的钨（W）螺柱之上形成第一低k电介质层; 通过所述第一低k电介质层形成开口以露出所述至少一个凹入的钨螺柱的上表面; 并用铜（Cu）填充开口。

    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES
    3.
    发明申请
    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的自对准图形蚀刻停止层

    公开(公告)号：US20110092069A1

    公开(公告)日：2011-04-21

    申请号：US12582137

    申请日：2009-10-20

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    IPC分类号： H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

    摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

    摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

    Self-aligned patterned etch stop layers for semiconductor devices
    6.
    发明授权
    Self-aligned patterned etch stop layers for semiconductor devices 失效
    用于半导体器件的自对准图案蚀刻停止层

    公开(公告)号：US08367544B2

    公开(公告)日：2013-02-05

    申请号：US12582137

    申请日：2009-10-20

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

    摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

    摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

    STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS
    8.
    发明申请
    STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
    半导体集成电路中降低PARASIIC电容的结构与方法

    公开(公告)号：US20090085210A1

    公开(公告)日：2009-04-02

    申请号：US11863724

    申请日：2007-09-28

    申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

    摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

    摘要翻译： 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

    Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits
    9.
    发明授权
    Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits 有权
    减小半导体集成电路中寄生电容的结构和方法

    公开(公告)号：US07825019B2

    公开(公告)日：2010-11-02

    申请号：US11863724

    申请日：2007-09-28

    申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    IPC分类号： H01L21/44

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

    摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

    摘要翻译： 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

    Metal interconnect and IC chip including metal interconnect
    10.
    发明授权
    Metal interconnect and IC chip including metal interconnect 有权
    金属互连和IC芯片包括金属互连

    公开(公告)号：US07851919B2

    公开(公告)日：2010-12-14

    申请号：US12701045

    申请日：2010-02-05

    申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

    发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

    IPC分类号： H01L21/40

    CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

    摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。