公开(公告)号：US08754357B2

公开(公告)日：2014-06-17

申请号：US13344095

申请日：2012-01-05

申请人： Guy Meynants ,  Jan Bogaerts

发明人： Guy Meynants ,  Jan Bogaerts

IPC分类号： H01J40/14 ,  H01L27/00

CPC分类号： H01L27/14612 ,  H04N5/353 ,  H04N5/3559 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/37452

摘要： A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

摘要翻译： 像素包括用于响应于入射辐射产生电荷的光敏元件。 传输门位于感光元件和感测节点之间，用于控制向感测节点传输电荷。 复位开关连接到感测节点，用于将感测节点复位到预定电压。 第一缓冲放大器具有连接到感测节点的输入端和连接到可操作以对感测节点的值进行采样的采样台的输出。 第二缓冲放大器具有连接到样品台的输入。 控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。 像素阵列同时暴露于辐射。 可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

公开(公告)号：US08569671B2

公开(公告)日：2013-10-29

申请号：US12408975

申请日：2009-03-23

申请人： Guy Meynants ,  Jan Bogaerts

发明人： Guy Meynants ,  Jan Bogaerts

IPC分类号： H01L27/00 ,  H01J40/14

CPC分类号： H01L27/14612 ,  H04N5/353 ,  H04N5/3559 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/37452

摘要： A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

摘要翻译： 像素包括用于响应于入射辐射产生电荷的感光元件和感测节点。 传输门位于感光元件和感测节点之间，用于控制电荷传递到感测节点。 复位开关连接到感测节点，用于将感测节点复位到预定电压。 第一缓冲放大器具有连接到感测节点的输入。 样本级连接到第一缓冲放大器的输出，并且可操作以对感测节点的值进行采样。 第二缓冲放大器具有连接到样品台的输入。 控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。 像素阵列同时暴露于辐射。 可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

公开(公告)号：US20120175499A1

公开(公告)日：2012-07-12

申请号：US13344095

申请日：2012-01-05

申请人： Guy Meynants ,  Jan Bogaerts

发明人： Guy Meynants ,  Jan Bogaerts

IPC分类号： H01L27/148 ,  H01L27/144

CPC分类号： H01L27/14612 ,  H04N5/353 ,  H04N5/3559 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/37452

摘要： A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

摘要翻译： 像素包括用于响应入射辐射产生电荷的光敏元件。 传输门位于感光元件和感测节点之间，用于控制向感测节点传输电荷。 复位开关连接到感测节点，用于将感测节点复位到预定电压。 第一缓冲放大器具有连接到感测节点的输入端和连接到可操作以对感测节点的值进行采样的采样台的输出。 第二缓冲放大器具有连接到样品台的输入。 控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。 像素阵列同时暴露于辐射。 可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

公开(公告)号：US20160112665A1

公开(公告)日：2016-04-21

申请号：US14515505

申请日：2014-10-15

申请人： Guy Meynants ,  Jan Bogaerts

发明人： Guy Meynants ,  Jan Bogaerts

IPC分类号： H04N5/374 ,  H01L27/146

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H04N5/23245 ,  H04N5/3559 ,  H04N5/37452

摘要： An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

摘要翻译： 图像传感器包括像素阵列，包括：钉扎光电二极管; 第一感知节点A; 第二感测节点B; 连接在钉扎光电二极管和第一感测节点A之间的传输门TX; 连接在电压基准线Vrst和第二感测节点B之间的第一复位晶体管M3; 连接在第一感测节点A和第二感测节点B之间的第二复位晶体管M4; 以及具有连接到第一感测节点A的输入端的缓冲放大器M1。控制逻辑被配置为以低转换增益模式和高转换增益模式操作像素。 在每个转换增益模式中，控制逻辑被布置成操作第一复位控制线RS1和第二复位控制线RS2中的一个，以在读出期间连续地接通第一复位晶体管M3和第二复位晶体管M4中的一个 的像素的操作周期。

公开(公告)号：US20140203956A1

公开(公告)日：2014-07-24

申请号：US14158818

申请日：2014-01-18

申请人： Guy Meynants ,  Bram WOLFS ,  Jan BOGAERTS

发明人： Guy Meynants ,  Bram WOLFS ,  Jan BOGAERTS

IPC分类号： H03M1/34

CPC分类号： H03M1/34 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

摘要翻译： 用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平 模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。 一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。 控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。 输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。

公开(公告)号：US09041579B2

公开(公告)日：2015-05-26

申请号：US14158818

申请日：2014-01-18

申请人： Guy Meynants ,  Bram Wolfs ,  Jan Bogaerts

发明人： Guy Meynants ,  Bram Wolfs ,  Jan Bogaerts

IPC分类号： H03M1/12 ,  H03M1/34 ,  H04N5/378 ,  H03M1/56

CPC分类号： H03M1/34 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

摘要翻译： 用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平 模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。 一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。 控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。 输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。

公开(公告)号：US08334491B2

公开(公告)日：2012-12-18

申请号：US12544755

申请日：2009-08-20

申请人： Jan Bogaerts ,  Guy Meynants

发明人： Jan Bogaerts ,  Guy Meynants

IPC分类号： H01L27/146 ,  H04N3/14

CPC分类号： H01L27/14603 ,  H01L27/14621 ,  H01L27/14641 ,  H04N5/347 ,  H04N5/3651 ,  H04N5/367 ,  H04N5/3745

摘要： A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

摘要翻译： 像素阵列包括以行和列排列的多个光敏元件以及用于读取感光元件的值的读出电路。 为一对相邻的感光元件提供共享读出电路。 共享读出电路的相邻实例相对于彼此交错。 对于具有用于一对光敏元件的共享读出电路的布局，共享读出电路的相邻实例被一列的水平距离和阵列的一行的垂直距离偏移。 共享读出电路可以在阵列的行或列中的一对相邻的光敏元件或在阵列中对角相邻的一对光敏元件。 由共享读出电路的交错实例产生的改善的产量和对称性。

公开(公告)号：US09666618B2

公开(公告)日：2017-05-30

申请号：US13537832

申请日：2012-06-29

申请人： Guy Meynants

发明人： Guy Meynants

IPC分类号： H01L27/146 ,  H04N5/353 ,  H04N5/3745 ,  H04N5/374

CPC分类号： H01L27/14609 ,  H04N5/3535 ,  H04N5/3741 ,  H04N5/3745

摘要： A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.

公开(公告)号：US09001245B2

公开(公告)日：2015-04-07

申请号：US12977935

申请日：2010-12-23

申请人： Xinyang Wang ,  Guy Meynants ,  Bram Wolfs

发明人： Xinyang Wang ,  Guy Meynants ,  Bram Wolfs

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/374 ,  H04N5/3745 ,  H04N5/355

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14641 ,  H01L27/14656 ,  H04N5/35572 ,  H04N5/3742 ,  H04N5/3745

摘要： A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element to the second charge conversion element via the second transfer gate.

摘要翻译： 像素结构包括用于响应于入射光而产生电荷的光敏元件。 第一传输门连接在光敏元件和第一电荷转换元件之间。 第二传输门连接在光敏元件和第二电荷转换元件之间。 输出级输出与第一充电转换元件的充电有关的第一值，并输出与第二充电转换元件的电荷相关的第二值。 控制器控制像素结构的操作并引起像素结构。 控制器使得像素结构在曝光期间获取感光元件上的电荷; 将在曝光期间中获取的电荷的第一部分经由第一传输门从光敏元件传送到第一电荷转换元件; 并且将在曝光期间获取的电荷的第二部分经由第二传输门从光敏元件传送到第二电荷转换元件。

公开(公告)号：US20090259421A1

公开(公告)日：2009-10-15

申请号：US12422148

申请日：2009-04-10

申请人： Valer Pop ,  Guido Dolmans ,  Guy Meynants

发明人： Valer Pop ,  Guido Dolmans ,  Guy Meynants

IPC分类号： G01R31/36

CPC分类号： G01R31/3648 ,  G01R31/3842

摘要： A system and method for estimating remaining run-time of an autonomous system by indirect measure is disclosed. In one aspect, the system includes a load circuit, an energy storage system (ESS) and an energy storage management system (ESM). The load circuit includes functional blocks. The ESS stores electric energy and is connected to the load circuit and configured to supply the varying electric current to the load circuit. The ESM is configured to estimate a remaining run-time of the autonomous system. The ESM includes an input connected to one of the functional blocks of the load circuit from which a first parameter being an indirect measure for the varying electric current supplied from the energy storage system to the load circuit is received. The ESM determines the remaining run-time from this first parameter.

摘要翻译： 公开了一种通过间接测量来估计自主系统的剩余运行时间的系统和方法。 一方面，该系统包括负载电路，能量存储系统（ESS）和能量存储管理系统（ESM）。 负载电路包括功能块。 ESS存储电能并且连接到负载电路并且被配置为向负载电路提供变化的电流。 ESM被配置为估计自主系统的剩余运行时间。 ESM包括连接到负载电路的功能块之一的输入端，从第一参数是从能量存储系统提供给负载电路的变化电流的间接测量被接收。 ESM从第一个参数确定剩余的运行时间。