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    NON-VOLATILE MEMORY DEVICE HAVING BOTTOM ELECTRODE
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE HAVING BOTTOM ELECTRODE 有权
    具有底电极的非易失性存储器件

    公开(公告)号：US20110193048A1

    公开(公告)日：2011-08-11

    申请号：US13087189

    申请日：2011-04-14

    申请人： Gyu-Hwan Oh ,  Sug-Woo Jung ,  Dong-Hyun Im

    发明人： Gyu-Hwan Oh ,  Sug-Woo Jung ,  Dong-Hyun Im

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2409 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/72 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    摘要： Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).

    摘要翻译： 提供了一种非易失性存储器件，其包括设置在衬底上并具有下部和上部的底部电极。 导电间隔件设置在底部电极的下部的侧壁上。 氮化物间隔物设置在导电间隔物的顶表面和底电极的上部的侧壁上。 电阻可变元件设置在底部电极和氮化物间隔物的上部。 底部电极的上部含有氮（N）。

    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
    6.
    发明申请
    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 有权
    堆叠半导体器件和制造方法

    公开(公告)号：US20080199991A1

    公开(公告)日：2008-08-21

    申请号：US12108591

    申请日：2008-04-24

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    摘要翻译： 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

    Methods of forming semiconductor devices having stacked transistors
    9.
    发明授权
    Methods of forming semiconductor devices having stacked transistors 失效
    形成具有层叠晶体管的半导体器件的方法

    公开(公告)号：US07435634B2

    公开(公告)日：2008-10-14

    申请号：US11398192

    申请日：2006-04-05

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84

    CPC分类号： H01L21/8221 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76898 ,  H01L27/0688 ,  Y10S257/903

    摘要： A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。 可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。 可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。 在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。 可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分 基质。 此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。 还讨论了相关设备。

    Nickel salicide process with reduced dopant deactivation
    10.
    发明授权
    Nickel salicide process with reduced dopant deactivation 有权
    具有减少掺杂剂钝化的镍硅化物工艺

    公开(公告)号：US07232756B2

    公开(公告)日：2007-06-19

    申请号：US10812003

    申请日：2004-03-30

    申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

    发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

    摘要翻译： 提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。 示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。 后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍 合金金属如钽，表现出减少的团聚和改善的温度稳定性。