公开(公告)号：US20160202936A1

公开(公告)日：2016-07-14

申请号：US14912681

申请日：2013-09-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre ,  Andrew R Wheeler

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F3/0685 ,  G06F3/0619 ,  G06F3/065 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/222 ,  G06F2212/60

Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

Abstract translation: 示例实现涉及管理存储器模块上的数据。 数据可以在存储器模块上的第一NVM和第二NVM之间传送。 第二NVM可能具有比第一NVM更高的存储容量和更长的访问延迟。 第一地址和第二地址之间的映射可以存储在存储器模块上的NVM中。 第一地址可以指数据存储在第一NVM中的位置。 第二地址可以指代数据被复制的第二NVM中的位置。

公开(公告)号：US11733932B2

公开(公告)日：2023-08-22

申请号：US14912681

申请日：2013-09-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre ,  Andrew R Wheeler

IPC: G06F3/06 ,  G06F12/121 ,  G06F12/1045 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/12

CPC classification number: G06F3/0685 ,  G06F3/065 ,  G06F3/0619 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/1054 ,  G06F12/121 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/222 ,  G06F2212/60

Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

公开(公告)号：US10762011B2

公开(公告)日：2020-09-01

申请号：US15880493

申请日：2018-01-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Blaine D Gaither ,  Robert J Brooks ,  Benjamin D Osecky ,  Kathryn A Evertson ,  Andrew R Wheeler ,  David Fisk

IPC: G06F13/16 ,  G06F13/42

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

公开(公告)号：US10540286B2

公开(公告)日：2020-01-21

申请号：US15967596

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S Milojicic ,  Keith Packard ,  Michael S. Woodacre ,  Andrew R Wheeler

IPC: G06F12/08 ,  G06F12/0837

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

公开(公告)号：US20160342333A1

公开(公告)日：2016-11-24

申请号：US15114427

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Andrew R Wheeler ,  Boris ZUCKERMAN ,  Greg ASTFALK ,  Russ W. HERRELL

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F3/0604 ,  G06F3/06 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/0223 ,  G06F12/0802 ,  G06F13/16 ,  G06F13/1694 ,  G06F13/4068 ,  G06F2212/60 ,  Y02D10/14 ,  Y02D10/151

Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.

Abstract translation: 统一的内存控制器（UMC）向本地主机发送和接收数据。 联电也可以通过使用地址映射器来管理数据的放置和检索。 UMC还可以选择性地向多个存储器位置提​​供电力。 UMC还可以基于可以利用存储在元数据存储位置中的属性的策略来管理数据布局。 该属性可以是描述正在管理的数据的属性。 UMC还可以使用自己的本地缓存，其可以存储由电路管理的数据的副本。