公开(公告)号：US20240146264A1

公开(公告)日：2024-05-02

申请号：US17976713

申请日：2022-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ryan Barnhill ,  Jacquelyn Mary Ingemi ,  Michael James Marshall ,  James S. Ignowski

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F2200/375

Abstract: One aspect can provide a direct current (DC) feedback circuit. The DC feedback circuit can include a gain path, a first feedback capacitor coupled, in parallel, to the gain path, and an input resistor coupled to an input of the gain path and the first feedback capacitor. The gain path can include an input stage with a pair of transconductance amplifiers, a gain stage with one or more amplifiers, and an output stage with at least one negative feedback amplifier.

公开(公告)号：US11265007B2

公开(公告)日：2022-03-01

申请号：US16938856

申请日：2020-07-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Peter Kurahashi ,  Dacheng Zhou ,  Michael James Marshall

IPC: H03M1/16 ,  H03M1/12

Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

公开(公告)号：US20240204789A1

公开(公告)日：2024-06-20

申请号：US18081490

申请日：2022-12-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

IPC: H03M1/06

CPC classification number: H03M1/0607

Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

公开(公告)号：US12132492B2

公开(公告)日：2024-10-29

申请号：US18081490

申请日：2022-12-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/38

CPC classification number: H03M1/0607 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/167 ,  H03M1/38

Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.