公开(公告)号：US11225086B2

公开(公告)日：2022-01-18

申请号：US16466408

申请日：2017-03-15

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Michael W Cumbie ,  Reynaldo V Villavelez ,  Chien-Hua Chen

IPC: B41J2/335

Abstract: A thermal contact device may include a thermal contact die embedded in a moldable material. The thermal contact die may include a number of resistors integrated into the thermal contact die, and a number of heater drivers integrated into the thermal contact die and electronically coupled to the resistors. The moldable material is coplanar with a thermal contact side of the thermal contact device. Further, the moldable material includes at least one gradient edge along a medium feed path.

公开(公告)号：US10752015B2

公开(公告)日：2020-08-25

申请号：US16323219

申请日：2016-10-20

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Reynaldo V Villavelez ,  Terry McMahon ,  Donald W Schulte

IPC: B41J2/345 ,  B41J2/335

Abstract: In some examples, a heater assembly for a pattern forming system includes a support, and heating elements mounted on the support, where the heating elements are to, in response to activation of the heating element, produce heat directed towards a target to form a pattern on the target. A heat sink is thermally connected to the heating elements and comprising a pattern of heat dissipation surfaces comprising channels to dissipate heat produced by the heating elements.

公开(公告)号：US20210283926A1

公开(公告)日：2021-09-16

申请号：US16466408

申请日：2017-03-15

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Michael W Cumbie ,  Reynaldo V Villavelez ,  Chien-Hua Chen

IPC: B41J2/335

Abstract: A thermal contact device may include a thermal contact die embedded in a moldable material. The thermal contact die may include a number of resistors integrated into the thermal contact die, and a number of heater drivers integrated into the thermal contact die and electronically coupled to the resistors. The moldable material is coplanar with a thermal contact side of the thermal contact device. Further, the moldable material includes at least one gradient edge along a medium feed path.

公开(公告)号：US20180006045A1

公开(公告)日：2018-01-04

申请号：US15543355

申请日：2015-01-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Lui Cheat Thin ,  Reynaldo V Villavelez

IPC: H01L27/11517 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11517 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42356 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.

公开(公告)号：US20170106648A1

公开(公告)日：2017-04-20

申请号：US15300613

申请日：2014-04-17

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning GE ,  Reynaldo V Villavelez

IPC: B41J2/045

CPC classification number: B41J2/04541 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/04586

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a bank of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the cells. A shift register circuit is coupled to at least one of the row select port and the column select port of each of the cells, the shift register circuit storing samples of an input signal responsive to a plurality of clock signals. A decoder is coupled to the shift register circuit to provide the input signal based on a logical combination of a plurality of data signals and at least a portion of the clock signals.

公开(公告)号：US11038033B2

公开(公告)日：2021-06-15

申请号：US15306740

申请日：2014-04-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Reynaldo V Villavelez ,  Ning Ge ,  Mun Hooi Yaow ,  Erik D Ness ,  David B Novak

IPC: H01L29/43 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02

Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

公开(公告)号：US20190248157A1

公开(公告)日：2019-08-15

申请号：US16323219

申请日：2016-10-20

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Reynaldo V Villavelez ,  Terry McMahon ,  Donald W Schulte

IPC: B41J2/345 ,  B41J2/335

CPC classification number: B41J2/345 ,  B41J2/3358

Abstract: In some examples, a heater assembly for a pattern forming system includes a support, and heating elements mounted on the support, where the heating elements are to, in response to activation of the heating element, produce heat directed towards a target to form a pattern on the target. A heat sink is thermally connected to the heating elements and comprising a pattern of heat dissipation surfaces comprising channels to dissipate heat produced by the heating elements.

公开(公告)号：US09776397B2

公开(公告)日：2017-10-03

申请号：US15300613

申请日：2014-04-17

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Reynaldo V Villavelez

IPC: B41J2/045

CPC classification number: B41J2/04541 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/04586

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a bank of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the cells. A shift register circuit is coupled to at least one of the row select port and the column select port of each of the cells, the shift register circuit storing samples of an input signal responsive to a plurality of clock signals. A decoder is coupled to the shift register circuit to provide the input signal based on a logical combination of a plurality of data signals and at least a portion of the clock signals.

公开(公告)号：US20170053993A1

公开(公告)日：2017-02-23

申请号：US15306740

申请日：2014-04-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Reynaldo V Villavelez ,  Ning GE ,  Mun Hooi YAOW ,  Erik D Ness ,  David B Novak

IPC: H01L29/423 ,  H01L49/02

Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

Abstract translation: 本主题涉及集成电路。 集成电路包括通过电介质层与第一金属层电容耦合的第一金属层和第二金属层。 此外，第二金属层包括电子泄漏路径，以在预定的泄漏时间段内提供来自第二金属层的电荷泄漏。