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公开(公告)号：US08901712B2
公开(公告)日：2014-12-02
申请号：US13798534
申请日：2013-03-13
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akira Kotabe
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0007 , G11C2213/71 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/144
Abstract: The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory.A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer.A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.
Abstract translation: 要解决的技术问题是通过简单的制造过程实现高密度，降低存储器的位成本。 根据本发明的第一方面的半导体存储器件包括串联连接在第一扩散层和金属线之间的可变电阻材料层和沟道层，从而分离金属线和沟道半导体层。 根据本发明的第二方面的半导体存储器件包括：可变电阻材料层，电连接在第一方向上彼此相对的沟道半导体层，并且在第二方向上电连接彼此相邻的沟道半导体层，其中多个 的沟道半导体层设置在第二方向上。
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公开(公告)号：US08976608B2
公开(公告)日：2015-03-10
申请号：US13910507
申请日：2013-06-05
Applicant: Hitachi, Ltd.
Inventor： Goichi Ono , Yusuke Kanno , Akira Kotabe
CPC classification number: G11C7/00 , G11C8/08 , G11C11/41 , G11C29/50 , G11C2029/1202
Abstract: A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
Abstract translation: 提供了一种半导体集成电路器件，其检测由随时间变化的器件变化引起的SRAM的操作误差。 在SRAM中，存储单元具有栅极连接到字线的转移MOS晶体管。 在存储单元的写入测试时，包括测试/正常操作选择电路和字线驱动电路的控制电路在写入测试数据之前的准备周期中向字线施加第三电压，此后，第一电压 到字线，以及在写入结束时到字线的第二电压。 由此，可以控制随时间变动的转移MOS晶体管的阈值电压。 因此，可以提高由于时间变化导致的SRAM的故障单元的检测效率。
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Patent Agency Ranking
公开(公告)号：US20130322188A1
公开(公告)日：2013-12-05
申请号：US13910507
申请日：2013-06-05
Applicant: Hitachi, Ltd.
Inventor： Goichi Ono , Yusuke Kanno , Akira Kotabe
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C8/08 , G11C11/41 , G11C29/50 , G11C2029/1202
Abstract: A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
Abstract translation: 提供了一种半导体集成电路器件，其检测由随时间变化的器件变化引起的SRAM的操作误差。 在SRAM中，存储单元具有栅极连接到字线的转移MOS晶体管。 在存储单元的写入测试时，包括测试/正常操作选择电路和字线驱动电路的控制电路在写入测试数据之前的准备周期中向字线施加第三电压，此后，第一电压 到字线，以及在写入结束时到字线的第二电压。 由此，可以控制随时间变动的转移MOS晶体管的阈值电压。 因此，可以提高由于时间变化导致的SRAM的故障单元的检测效率。
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公开(公告)号：US20130292630A1
公开(公告)日：2013-11-07
申请号：US13798534
申请日：2013-03-13
Applicant: HITACHI, LTD.
Inventor： Yoshitaka Sasago , Akira Kotabe
IPC: H01L27/24
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0007 , G11C2213/71 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/144
Abstract: The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory.A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer.A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.
Abstract translation: 要解决的技术问题是通过简单的制造过程实现高密度，降低存储器的位成本。 根据本发明的第一方面的半导体存储器件包括串联连接在第一扩散层和金属线之间的可变电阻材料层和沟道层，从而分离金属线和沟道半导体层。 根据本发明的第二方面的半导体存储器件包括：可变电阻材料层，电连接在第一方向上彼此相对的沟道半导体层，并且在第二方向上电连接彼此相邻的沟道半导体层，其中多个 的沟道半导体层设置在第二方向上。
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公开(公告)号：US09361978B2
公开(公告)日：2016-06-07
申请号：US14421822
申请日：2012-09-20
Applicant: Hitachi, Ltd.
Inventor： Nobuhiro Shiramizu , Satoru Hanzawa , Akira Kotabe
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/003 , G11C2013/0071 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/144
Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
Abstract translation: 提供本发明，以通过串联连接多个存储单元而获得的半导体存储器件中的每一层抑制提供给存储元件的电流不变化。 根据本发明的半导体存储器件包括串联连接在第一信号线和第二信号线之间的多个存储器单元，并分别向包括在存储器单元中的选择晶体管中的至少两个提供不同的栅极电压（参见 至图2）。
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公开(公告)号：US20150221367A1
公开(公告)日：2015-08-06
申请号：US14421822
申请日：2012-09-20
Applicant: Hitachi, Ltd.
Inventor： Nobuhiro Shiramizu , Satoru Hanzawa , Akira Kotabe
IPC: G11C13/00
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/003 , G11C2013/0071 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/144
Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
Abstract translation: 提供本发明，以通过串联连接多个存储单元而获得的半导体存储器件中的每一层抑制提供给存储元件的电流不变化。 根据本发明的半导体存储器件包括串联连接在第一信号线和第二信号线之间的多个存储器单元，并分别向包括在存储器单元中的选择晶体管中的至少两个提供不同的栅极电压（参见 至图2）。
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公开(公告)号：US20140154790A1
公开(公告)日：2014-06-05
申请号：US14122206
申请日：2011-05-31
Applicant: HITACHI, LTD.
Inventor： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
IPC: C12Q1/68
CPC classification number: C12Q1/68 , C12Q1/6869 , G01N33/48721 , C12Q2565/631
Abstract: Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).
Abstract translation: 提供了基于具有低值和广泛分布的电流的测量结果来识别通过纳米颗粒路径的生物分子的组成的装置。 该生物分子信息分析装置通过对通过第一电极和第二电极之间的间隙的生物分子施加电场来获得电流值，并且通过对当前值进行积分并与参考值进行比较来识别生物分子的结构（ 参见图1）。
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