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公开(公告)号：US20180151076A1
公开(公告)日：2018-05-31
申请号：US15578445
申请日：2016-06-13
申请人： Hitachi, Ltd.
发明人： Teppei HIROTSU
摘要： Provided is a travel command generation device that generates, on the basis of an existence probability distribution for a plurality of obstacles, travel commands to avoid collision between the plurality of obstacles and a host vehicle, wherein the speed of collision probability computation is enhanced. On the basis of the existence probability distribution for the plurality of obstacles, a collision probability table is generated, for which a movement distance L on a fixed trajectory and a time T are input and the probabilities of collision between the plurality of obstacles and the host vehicle are output; and on the basis of the collision probability table, travel commands are generated for avoiding collision between the plurality of obstacles and the host vehicle.
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公开(公告)号：US20170082984A1
公开(公告)日：2017-03-23
申请号：US15311678
申请日：2015-05-07
申请人： Hitachi Ltd.
IPC分类号： G05B11/36
CPC分类号： G05B11/36 , G05B13/048
摘要： The objective of the present invention is to increase reliability in an electronic control device when speculative execution is performed, by reducing the risk of erroneous control by the electronic control device, said erroneous control being due to speculative execution failures (such as failures to predict a future state or failure to complete a control calculation due to the execution of an advanced control calculation) which are generated when speculative execution is performed using limited hardware resources in an electronic control device having a control period restriction. Therefore, this electronic control device, which performs a calculation in accordance with one or more external inputs, and outputs a calculation result by a prescribed time, has one or more first calculation units that perform a calculation using a current input, and one or more second calculation units that perform a calculation using a prior input that been input at a point in time prior to the current input.
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公开(公告)号：US20180278254A1
公开(公告)日：2018-09-27
申请号：US15546694
申请日：2015-01-28
申请人： Hitachi, Ltd.
发明人： Teruaki SAKATA , Tsutomu YAMADA , Teppei HIROTSU
IPC分类号： H03K19/177 , G06F11/10 , G11C29/52 , G01R31/317
摘要： To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.
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公开(公告)号：US20160241247A1
公开(公告)日：2016-08-18
申请号：US15025821
申请日：2013-09-30
申请人： HITACHI, LTD.
发明人： Yusuke KANNO , Nobuyasu KANEKAWA , Kotaro SHIMAMURA , Tadanobu TOBA , Teppei HIROTSU , Tsutomu YAMADA
IPC分类号： H03K19/177 , H03K19/21
CPC分类号： H03K19/17764 , H03K19/17728 , H03K19/1776 , H03K19/21
摘要： An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability for a failure of the configuration memory is higher than reliability in the other area.
摘要翻译： 本发明的目的是提供一种具有高抗错误性的高可靠/高安全性的可编程逻辑器件。 本发明提供一种具有多个配置存储器的可编程逻辑器件。 配置存储器被分成多个区域并且被布置，并且多个区域的一部分被设置为高可靠性区域，其中配置存储器的故障的可靠性高于其他区域中的可靠性。
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公开(公告)号：US20210200926A1
公开(公告)日：2021-07-01
申请号：US16755705
申请日：2018-03-05
申请人： HITACHI, LTD.
发明人： Teruaki SAKATA , Teppei HIROTSU
摘要： A circuit generation device that implements a standard function and a degeneration function has a first operation synthesis function of generating a circuit description based on a system operation description, there are provided a degenerate parameter extraction function of extracting a degenerate parameter from the operation description, a degeneration parameter change function of changing a value of the degeneration parameter, a second operation synthesis function of generating a degeneration circuit description based on the operation description and the degeneration parameter value, and a determination function of determining whether the performance of the degeneration circuit description satisfies a constraint condition based on the circuit description. When the determination function determines that the degeneration circuit description does not satisfy the constraint condition, the second operation synthesis function is executed after the value of the degeneration parameter is changed by the degeneration parameter change function.
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公开(公告)号：US20200050164A1
公开(公告)日：2020-02-13
申请号：US16607296
申请日：2017-04-25
申请人： HITACHI, LTD.
发明人： Teruaki SAKATA , Teppei HIROTSU
IPC分类号： G05B19/042 , G06F11/14
摘要： In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.
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公开(公告)号：US20190325311A1
公开(公告)日：2019-10-24
申请号：US16470633
申请日：2017-01-10
申请人： Hitachi, Ltd.
摘要： The present invention addresses the problem of implementing a neural network using a small-scale circuit by simplifying the multiplication of the input data by weight data. The neural network circuit according to the present invention is configured from: a means for multiplying input data by a rounded value of the mantissa part of weight data; a means for shifting the multiplication result by the number of bits of the rounded value; a means for adding the shifted result to the original input data; and a means for shifting the addition result by the number of bits of the exponent part of the weight.
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公开(公告)号：US20190187675A1
公开(公告)日：2019-06-20
申请号：US16301920
申请日：2017-04-13
申请人： Hitachi, Ltd.
IPC分类号： G05B23/02
CPC分类号： G05B23/0221 , G05B23/02
摘要： Provided is a method of detecting and preventing soft errors without performing multiplexing. As a result, it is possible to improve reliability of a device while suppressing an increase in mounting cost and reduction in operation speed accompanied with it. A diagnosis system includes an initial parameter generation unit which generates a plurality of initial parameters predicted on the basis of an external input; an operation unit which has a plurality of operators operating optimal solutions to the initial parameters by using an evaluation function describing a control object; and a diagnosis unit which diagnoses the operation unit on the basis of an output of the operation unit. When an optimal solution candidate giving an evaluation value deviating from a value taken by each evaluation value by a constant threshold or more among evaluation values corresponding to the optimal solutions to the initial parameters is found, the diagnosis unit diagnoses an error of the operation unit.
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