Asynchronous pulse domain to synchronous digital domain converter

    公开(公告)号:US09843339B1

    公开(公告)日:2017-12-12

    申请号:US15248358

    申请日:2016-08-26

    CPC分类号: G06F1/04 G06F1/12

    摘要: An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

    Dual edge pulse de-multiplexer with equalized path delay
    4.
    发明授权
    Dual edge pulse de-multiplexer with equalized path delay 有权
    具有均衡路径延迟的双边沿脉冲解复用器

    公开(公告)号:US09484918B1

    公开(公告)日:2016-11-01

    申请号:US14834837

    申请日:2015-08-25

    IPC分类号: H03K19/003 H03K19/00

    摘要: A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

    摘要翻译: 脉冲域1至2N解复用器具有(i)一对N级计数器,每个N级计数器响应于脉冲域中的输入脉冲序列,其中一个计数器响应于输入脉冲串中的脉冲的前沿, 另一个计数器响应输入脉冲串中的脉冲的后沿,以及(ii)响应于该对计数器计数的状态的控制逻辑,包括2N个门装置的控制逻辑,2N个 门结构产生脉冲域1至2N解复用器的输出信号。