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公开(公告)号：US20190392871A1
公开(公告)日：2019-12-26
申请号：US16559959
申请日：2019-09-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Enyi Yao , Chen-Xiong Zhang
IPC: G11C5/14 , G11C11/4074 , G11C16/30 , G11C7/10 , G05F1/575
Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.
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公开(公告)号：US11119732B2
公开(公告)日：2021-09-14
申请号：US17004893
申请日：2020-08-27
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jian Zhang , Yangyang Tang
Abstract: A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.
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3.发明授权Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it 有权具有容错性能的通用纠错电路，以及应用它的解码器和三模块冗余电路公开(公告)号：US09577960B2
公开(公告)日：2017-02-21
申请号：US14581570
申请日：2014-12-23
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Chen-Xiong Zhang
CPC classification number: H04L49/557 , G06F11/187 , H03K19/23 , H03M13/1105 , H03M13/27 , H03M13/43 , H03M13/6508
Abstract: A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k-1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok-2, and Ok-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok-1=I2k-1 if Ok-2=I2k-1, and Ok-1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.
Abstract translation: 具有容错性的通用纠错电路包括由逻辑门执行的具有容错性质的纠错单元，其中具有容错性质的纠错单元的数字输入信号分别为I0，I1。 。 。 ，I2k-1和I2k，具有容错性质的纠错单元的数字输出信号分别为O0，O1，...。 。 。 ，Ok-2和Ok-1，并且数字输入信号和数字输出信号属于集合{0,1}，其中k是正整数。 当k = 1时，具有容错性质的纠错单元被配置为：如果I0 = I1，则设置O0 = I0，否则为O0 = I2; 并且当k> 1时，如果Ok-2 = I2k-1，则设置Ok-1 = I2k-1，否则为Ok-1 = I2k。 由于输入和输出之间的逻辑关系是唯一确定的，所以具有容错特性的纠错电路可以仅由逻辑门来实现。
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公开(公告)号：US20210166735A1
公开(公告)日：2021-06-03
申请号：US17171333
申请日：2021-02-09
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Enyi Yao , Chen-Xiong Zhang
IPC: G11C5/14 , G05F1/575 , G11C7/10 , G11C11/4074 , G11C16/30
Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.
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公开(公告)号：US10984839B2
公开(公告)日：2021-04-20
申请号：US16559959
申请日：2019-09-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Enyi Yao , Chen-Xiong Zhang
Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.
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Patent Agency Ranking
公开(公告)号：US11120845B2
公开(公告)日：2021-09-14
申请号：US17171333
申请日：2021-02-09
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Enyi Yao , Chen-Xiong Zhang
Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.
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公开(公告)号：US20170230005A1
公开(公告)日：2017-08-10
申请号：US15581445
申请日：2017-04-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Chen-Xiong Zhang
CPC classification number: H03F1/0205 , H03F1/38 , H03F3/45183 , H03F3/45219 , H03F3/45273 , H03F2200/135 , H03F2200/153 , H03F2200/513 , H03F2200/87 , H03F2203/45028 , H03F2203/45036 , H03F2203/45051 , H03F2203/45054 , H03F2203/45114 , H03F2203/45124 , H03F2203/45134 , H03F2203/45221 , H03F2203/45281 , H03F2203/45288 , H03F2203/45342
Abstract: A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.
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8.发明申请Universal Error-Correction Circuit with Fault-Tolerant Nature, and Decoder and Triple Modular Redundancy Circuit That Apply It 有权具有容错性的通用误差校正电路，以及应用它的解码器和三重模块化冗余电路公开(公告)号：US20150188580A1
公开(公告)日：2015-07-02
申请号：US14581570
申请日：2014-12-23
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Chen-Xiong Zhang
CPC classification number: H04L49/557 , G06F11/187 , H03K19/23 , H03M13/1105 , H03M13/27 , H03M13/43 , H03M13/6508
Abstract: A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k−1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok−2, and Ok−1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok−1=I2k−1 if Ok−2=I2k−1, and Ok−1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.
Abstract translation: 具有容错性的通用纠错电路包括由逻辑门执行的具有容错性质的纠错单元，其中具有容错性质的纠错单元的数字输入信号分别为I0，I1。 。 。 ，I2k-1和I2k，具有容错性质的纠错单元的数字输出信号分别为O0，O1，...。 。 。 ，Ok-2和Ok-1，并且数字输入信号和数字输出信号属于集合{0,1}，其中k是正整数。 当k = 1时，具有容错性质的纠错单元被配置为：如果I0 = I1，则设置O0 = I0，否则为O0 = I2; 并且当k> 1时，如果Ok-2 = I2k-1，则设置Ok-1 = I2k-1，否则为Ok-1 = I2k。 由于输入和输出之间的逻辑关系是唯一确定的，所以具有容错特性的纠错电路可以仅由逻辑门来实现。
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公开(公告)号：US20190273427A1
公开(公告)日：2019-09-05
申请号：US16416778
申请日：2019-05-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yangyang Tang , Jian Zhang , Hu Liu , Cong Yao , Xinru Wang , Chen-Xiong Zhang
Abstract: A voltage regulation circuit includes an obtainer that is configured to obtain load information of a corresponding load and output the load information to a corresponding controller. The corresponding controller generates a switch control signal based on the load information and outputs the switch controller to at least one switch. The at least one switch regulates, based on the accurate switch control signal, a voltage input to the corresponding load.
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公开(公告)号：US10394262B2
公开(公告)日：2019-08-27
申请号：US15859117
申请日：2017-12-29
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xinru Wang , Yangyang Tang , Xin Jin , Zhonglei Yang
Abstract: A voltage regulation method, a controller, and a chip are provided. In the method, a controller receives a digital first status representation value sent by a sensor; the controller determines, according to the first status representation value and at least one of a second status representation value or a first expected value, whether to regulate the supply voltage of the load, where the second status representation value represents a node voltage that is at a previous moment and that is of the detection point of the load, and the first expected value represents an expected value of a node voltage of the detection point; and when determining to regulate the supply voltage of the load, the controller sends a digital control signal to a power gating array, to control the power gating array to regulate the supply voltage.
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