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    METHOD AND SYSTEM OF DESIGNING MEMRISTOR-BASED NAIVE BAYES CLASSIFIER AND CLASSIFIER
    1.
    发明公开
    METHOD AND SYSTEM OF DESIGNING MEMRISTOR-BASED NAIVE BAYES CLASSIFIER AND CLASSIFIER 审中-公开

    公开(公告)号：US20230334824A1

    公开(公告)日：2023-10-19

    申请号：US17775591

    申请日：2021-05-07

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Huajun SUN ,  Zuopai ZHOU ,  Li LI ,  Xiangshui MIAO

    IPC: G06V10/764 ,  G06V10/94

    CPC classification number: G06V10/764 ,  G06V10/955

    Abstract: A method and a system of designing a memristor-based naive Bayes classifier and a classifier belonging to the field of information technology are provided. The method includes: constructing a naive Bayes classifier including a memristor array of M rows by 2N columns, where M is the number of classification types, and N is the number of pixels in a picture; calculating the number hj,2i−1 of the pixel value of 0 and the number hj,2i of the pixel value of 1 in an ith pixel in the jth training sample, where j=1, 2, . . . , and M; and applying hj,2i−1 pulses to a memristor Rj,2i−1 in a jth row and a 2i−1th column to modulate the conductance of the memristor Rj,2i−1 and applying hj,2i pulses to a memristor Rj,2i in the jth row and a 2ith column to modulate the conductance of the memristor Rj,2i.

    NON-VOLATILE BOOLEAN LOGIC OPERATION CIRCUIT AND OPERATION METHOD THEREOF
    2.
    发明申请
    NON-VOLATILE BOOLEAN LOGIC OPERATION CIRCUIT AND OPERATION METHOD THEREOF 有权
    非挥发性BOOLEAN逻辑操作电路及其操作方法

    公开(公告)号：US20160020766A1

    公开(公告)日：2016-01-21

    申请号：US14867030

    申请日：2015-09-28

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui MIAO ,  Yaxiong ZHOU ,  Yi LI ,  Huajun SUN

    IPC: H03K19/00 ,  H03K19/20

    CPC classification number: H03K19/0002 ,  H03K19/0021 ,  H03K19/0813 ,  H03K19/20

    Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

    Abstract translation: 一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端 第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。 第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。 第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。 第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。

    NONVOLATILE LOGIC GATE CIRCUIT BASED ON PHASE CHANGE MEMORY
    4.
    发明申请
    NONVOLATILE LOGIC GATE CIRCUIT BASED ON PHASE CHANGE MEMORY 有权
    基于相位变化记忆的非诺基亚逻辑门电路

    公开(公告)号：US20150236697A1

    公开(公告)日：2015-08-20

    申请号：US14706004

    申请日：2015-05-07

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG ,  Lei XU ,  Huajun SUN ,  Xiaomin CHENG

    IPC: H03K19/003 ,  H03K19/177 ,  H03K19/20 ,  G11C13/00 ,  H03K19/173

    CPC classification number: H03K19/00346 ,  G11C13/0004 ,  G11C13/004 ,  H03K19/1733 ,  H03K19/17724 ,  H03K19/20

    Abstract: A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.

    Abstract translation: 一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端 和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端， 第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。

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