公开(公告)号：US20150318040A1

公开(公告)日：2015-11-05

申请号：US14800693

申请日：2015-07-15

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG ,  Lei XU ,  Huajun SUN ,  Xiaohua XU

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0004 ,  G11C11/005 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/00 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144

Abstract: A joint short-time and long-time storage device, including a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer. The first electrode layer is made of inert conductive metal, the second electrode layer is made of active conductive metal, and the functional material layer is made of chalcogenide.

Abstract translation: 一种联合的短时和长时间存储装置，包括第一电极层，连接到第一电极层的功能材料层和连接到功能材料层的第二电极层。 第一电极层由惰性导电金属制成，第二电极层由有源导电金属制成，功能材料层由硫族化物制成。

公开(公告)号：US20150131355A1

公开(公告)日：2015-05-14

申请号：US14601216

申请日：2015-01-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Lei XU ,  Yingpeng ZHONG

IPC: G11C15/04 ,  G11C5/06

CPC classification number: G11C15/046 ,  G11C11/54 ,  G11C13/0007

Abstract: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.

Abstract translation: 一种包括第一忆阻器，第二忆阻器，固定值电阻器R和操作比较器的关联存储器电路。 第一忆阻器的一个端子是相关存储器电路的第一输入端，并且第一忆阻器的另一端连接到操作比较器的第一输入端。 第二忆阻器的一个端子是关联存储器电路的第二输入端，并且第二忆阻器的另一端连接到运算比较器的第一输入端。 固定值电阻的一端连接到运算比较器的第一输入端，固定值电阻的另一端连接到地。 操作比较器的第二输入端连接到参考电压。

公开(公告)号：US20150381181A1

公开(公告)日：2015-12-31

申请号：US14849621

申请日：2015-09-10

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG

IPC: H03K19/08 ,  G11C11/16 ,  G11C13/00 ,  H03K19/177

CPC classification number: H03K19/08 ,  G11B5/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0097 ,  H03K19/1776 ,  H03K19/18

Abstract: A non-volatile logic device, including: a substrate, a magnetic head, a base electrode, an insulating layer, a phase-change magnetic film, and a top electrode. The substrate includes a silicon substrate and an active layer attached to the silicon substrate. The base electrode includes an N-type silicon layer, a P-type silicon layer and a heating layer, the N-type silicon layer and the P-type silicon layer constitute a PN diode structure, and the size of the heating layer is smaller than that of the P-type silicon layer. The phase-change magnetic film is deposited on the insulating layer and is electrically contacted with the heating layer. The top electrode and the base electrode are connected to an external electrical pulse signal, and an external magnetic field parallel to a two dimensional plane of the phase-change magnetic film is applied to the non-volatile logic device.

Abstract translation: 一种非易失性逻辑器件，包括：基板，磁头，基极，绝缘层，相变磁性膜和顶部电极。 衬底包括硅衬底和附着到硅衬底的有源层。 基极包括N型硅层，P型硅层和加热层，N型硅层和P型硅层构成PN二极管结构，加热层的尺寸较小 比P型硅层高。 相变磁性膜沉积在绝缘层上并与加热层电接触。 顶部电极和基极连接到外部电脉冲信号，并且将平行于相变磁性膜的二维平面的外部磁场施加到非易失性逻辑器件。

公开(公告)号：US20150236697A1

公开(公告)日：2015-08-20

申请号：US14706004

申请日：2015-05-07

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG ,  Lei XU ,  Huajun SUN ,  Xiaomin CHENG

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/20 ,  G11C13/00 ,  H03K19/173

CPC classification number: H03K19/00346 ,  G11C13/0004 ,  G11C13/004 ,  H03K19/1733 ,  H03K19/17724 ,  H03K19/20

Abstract: A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.

Abstract translation: 一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端 和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端， 第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。