公开(公告)号：US20060186108A1

公开(公告)日：2006-08-24

申请号：US11413174

申请日：2006-04-28

申请人： Hag Kim ,  Myeong Kang

发明人： Hag Kim ,  Myeong Kang

IPC分类号： A21B1/22 ,  A21B1/00 ,  F27D11/00

CPC分类号： F24C15/325 ,  F24C7/06 ,  F24C7/087 ,  F24C15/006 ,  F24C15/04 ,  H05B6/642 ,  H05B6/6482

摘要： An electric oven includes a cooking cavity surrounded by an inner case and being openable by a door; a first heater for heating the cooking cavity; at least one supplemental heater for heating the cooking cavity; and a controller operating the first heater to generate heat when starting cooking and selectively operating the at least one supplemental heater during cooking.

摘要翻译： 电烤炉包括由内壳包围并可由门打开的烹饪腔; 用于加热烹饪腔的第一加热器; 至少一个用于加热烹饪腔的补充加热器; 以及控制器，其在开始烹饪时操作所述第一加热器以产生热量并且在烹饪期间选择性地操作所述至少一个补充加热器。

公开(公告)号：US20060214939A1

公开(公告)日：2006-09-28

申请号：US11390100

申请日：2006-03-28

申请人： Hag Kim ,  Duck Lee ,  Han Choi

发明人： Hag Kim ,  Duck Lee ,  Han Choi

IPC分类号： G09G5/00

CPC分类号： G06T1/20 ,  G06T15/04

摘要： Provided is a three-dimensional (3D) graphic processing system and method capable of utilizing camera preview images in which the camera preview images are stored in a texture memory and then the stored camera preview images are used as a texture in a 3D graphic processor. The camera preview images are stored in a texture memory and then the stored camera preview images are used as a texture in a 3D graphic processor, in a manner that an extended function can be supported through a mutual operation of a preview processor and a graphic processor. The camera preview is displayed on the moving polygonal plane to which a near-and-far sense is applied, or the camera image is used as a background texture to then enable 3D objects to be drawn on the background texture. As a result, games with real feeling can be developed in a manner that 3D contents can be realized using real images as a background.

摘要翻译： 提供了一种能够利用相机预览图像存储在纹理存储器中的相机预览图像，然后将存储的相机预览图像用作3D图形处理器中的纹理的三维（3D）图形处理系统和方法。 相机预览图像被存储在纹理存储器中，然后存储的相机预览图像被用作3D图形处理器中的纹理，其方式是可以通过预览处理器和图形处理器的相互操作来支持扩展功能 。 相机预览显示在应用了远近感觉的移动多边形平面上，或者将相机图像用作背景纹理，然后使3D对象在背景纹理上绘制。 结果，可以以使用真实图像作为背景来实现3D内容的方式来开发具有真实感觉的游戏。

公开(公告)号：US20050248163A1

公开(公告)日：2005-11-10

申请号：US10524409

申请日：2004-07-13

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： F24C15/02 ,  E05C3/06

CPC分类号： F24C15/022 ,  E05B47/0012 ,  E05B47/026 ,  E05B63/0052 ,  E05B2047/0051 ,  E05B2063/0026 ,  H05B6/6417 ,  Y10T292/1082

摘要： A door opening and closing system for a electric oven is provided. The system includes: at least one latch provided at one side surface of a door; a door interlocking structure having a rotary lever, a switch and an elastic spring to sense opening and closing of the door, the rotary lever being pushed by the latch to rotate about one side, the switch sequentially contacting with the rotary lever, and the elastic spring allowing the rotary lever to be supported in one direction; and a door locking structure having a motor, a rotary unit and a latch guide unit, the motor rotating after it is sensed that the door is closed by the door interlocking structure, the rotary unit engaged with and rotated about a rotary shaft of the motor, and the latch guide unit being associated with the rotary unit to change a rotation motion of the rotary unit into a straight-line motion such that the door is latched to the latch to prevent an erroneous opening of the door.

摘要翻译： 提供一种用于电烤箱的门开闭系统。 该系统包括：设置在门的一个侧表面处的至少一个闩锁; 门互锁结构具有旋转杆，开关和用于检测门的打开和关闭的弹性弹簧，所述旋转杆被所述闩锁推动以围绕一侧旋转，所述开关顺序地与所述旋转杆接触，并且所述弹性 允许旋转杆沿一个方向支撑的弹簧; 以及具有电动机，旋转单元和闩锁引导单元的门锁结构，所述电动机在感测到门被门互锁结构关闭之后旋转，所述旋转单元与电动机的旋转轴接合并围绕电动机旋转 并且所述闩锁引导单元与所述旋转单元相关联，以将所述旋转单元的旋转运动改变为直线运动，使得所述门闩锁到所述闩锁以防止所述门的错误打开。

公开(公告)号：US20050142771A1

公开(公告)日：2005-06-30

申请号：US11021638

申请日：2004-12-24

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L21/2022 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion implantation areas having different depths in a first conductive type semiconductor substrate; forming a pillar by selectively etching the first conductive type semiconductor substrate; sequentially depositing a gate insulating layer and a conductive layer for a gate electrode on the first conductive type semiconductor substrate including the pillar; forming the gate electrode by selectively patterning the conductive layer; and forming second conductive type source/drain impurity ion areas in the first conductive type semiconductor substrate corresponding to the top of the pillar and both sidewalls of the pillar.

摘要翻译： 公开了晶体管及其制造方法，以在杂质区域均匀地提供杂质离子，并且防止短沟道效应，其中制造晶体管的方法包括形成具有不同的多个沟道离子注入区域的步骤 深度在第一导电类型半导体衬底中; 通过选择性地蚀刻所述第一导电类型半导体衬底来形成柱; 在包括所述柱的所述第一导电类型半导体衬底上依次沉积栅极绝缘层和用于栅电极的导电层; 通过选择性地图案化导电层来形成栅电极; 以及在所述第一导电类型半导体衬底中形成与所述柱的顶部和所述柱的两个侧壁相对应的第二导电型源极/漏极杂质离子区域。

公开(公告)号：US20050130381A1

公开(公告)日：2005-06-16

申请号：US11010157

申请日：2004-12-10

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1045

摘要： Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on the sidewalls of the gate electrode; implanting ions of the second conductive type into the active region to form second source/drain regions; implanting halo ions into the active region; activating ions in the source/drain regions by conducting a first thermal process; and moving the halo ions toward the surface of the channel under the gate electrode by conducting a second thermal process.

摘要翻译： 公开了用于稳定NMOS晶体管中的阈值电压的方法。 所公开的方法包括：在第一导电类型的衬底中的有源区上形成栅电极; 将第二导电类型的离子注入到有源区中以形成LDD区; 在栅电极的侧壁上形成间隔物; 将所述第二导电类型的离子注入到所述有源区中以形成第二源极/漏极区; 将卤素离子注入活性区; 通过进行第一热处理激活源/漏区中的离子; 并且通过进行第二热处理将卤素离子移向栅电极下方的沟道的表面。

公开(公告)号：US20050202635A1

公开(公告)日：2005-09-15

申请号：US11020095

申请日：2004-12-27

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/7827

摘要： A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area. The method also includes forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area, sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer, and forming the first gate electrode by selectively patterning the conductive layer. The method further includes forming an insulating interlayer on an entire surface of the substrate including the first gate electrode, forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area, and forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.

摘要翻译： 一种用于制造垂直晶体管的方法，包括在半导体衬底中形成第一结区，通过在衬底中使用外延生长形成多晶硅层，在多晶硅层中形成第二结区，并在多晶硅层中形成插塞结的区域 所述插头连接区域与所述第一接合区域电连接。 该方法还包括通过选择性地蚀刻和去除多晶硅层以暴露出第一结区域，顺序地在沟槽和多晶硅层上淀积用于第一栅电极的栅极绝缘层和导电层，形成沟槽，以及形成第一栅极 电极通过选择性地图案化导电层。 该方法还包括在包括第一栅极的基板的整个表面上形成绝缘中间层，形成用于暴露第一接合区域的预定部分，第一栅电极和插塞接合区域的通孔，以及形成源极/ 漏极电极和第二栅极电极，其通过在通孔内形成金属层而分别与第一接合区域，第一栅极电极和插塞接合区域连接。

公开(公告)号：US20050136607A1

公开(公告)日：2005-06-23

申请号：US11021731

申请日：2004-12-23

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： Methods of fabricating a semiconductor devices are disclosed. One example method includes forming a gate insulating layer and a gate electrode on a semiconductor substrate; forming first halo implant regions under the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming low concentration impurity regions for LDD regions under sides of the gate electrode in the semiconductor substrate by implanting second conduction type impurities at a low concentration; forming second halo implant regions under sides of the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming high concentration impurity regions for source/drain regions in the semiconductor substrate by implanting second conduction type impurities; and forming junction compensation ion regions between the high concentration impurity regions and the second halo implant regions by implanting first conduction type impurities.

摘要翻译： 公开了制造半导体器件的方法。 一种示例性方法包括在半导体衬底上形成栅极绝缘层和栅电极; 通过注入第一导电型杂质在半导体衬底中的栅电极下形成第一晕环注入区; 通过以低浓度注入第二导电型杂质，在半导体衬底中的栅电极侧面的LDD区域形成低浓度杂质区; 通过注入第一导电型杂质在半导体衬底中的栅电极的侧面上形成第二晕环注入区; 通过注入第二导电型杂质在半导体衬底中形成用于源极/漏极区的高浓度杂质区; 以及通过注入第一导电型杂质在高浓度杂质区和第二晕环注入区之间形成结补偿离子区。

公开(公告)号：US20060168156A1

公开(公告)日：2006-07-27

申请号：US11290073

申请日：2005-11-30

申请人： Seung Bae ,  Jin Kim ,  Seung Jeon ,  Hag Kim ,  Myung Kim

发明人： Seung Bae ,  Jin Kim ,  Seung Jeon ,  Hag Kim ,  Myung Kim

IPC分类号： G06F15/177

CPC分类号： H04L67/1008 ,  H04L67/1002 ,  Y10S707/99939

摘要： A hierarchical system configuration method and an integrated scheduling method for offering a multimedia streaming service on a two-level double cluster system are provided. The hierarchical system configuration method includes the steps of: determining whether one server node exists; if one server node exists, determining whether one virtual server node/specific network storing and merging block exists; and if one virtual server node/specific network storing and merging block exists, setting a system configuration mode for configuring a single virtual server node based multimedia streaming server system and determining a representative network address of a current system, wherein depending on a scale and a characteristic of the multimedia streaming service, a hierarchical multimedia streaming server system is configured into a single virtual server node based system, which is a minimum-scale, a mono-level single virtual cluster based system, which is a medium-scale, and a two-level double cluster based system, which is a maximum-scale.

公开(公告)号：US20060136487A1

公开(公告)日：2006-06-22

申请号：US11300968

申请日：2005-12-15

申请人： Jin Kim ,  Seung Bae ,  Sang Woo ,  Yuhyeon Bak ,  Hag Kim ,  Myung Kim

发明人： Jin Kim ,  Seung Bae ,  Sang Woo ,  Yuhyeon Bak ,  Hag Kim ,  Myung Kim

IPC分类号： G06F17/00

CPC分类号： H04L67/06 ,  H04L67/1095 ,  H04L67/1097

摘要： A clustering apparatus and method for content delivery system are provided. The clustering apparatus includes: a local server for performing operations as a dedicated server providing a stream service by being connected to a cluster; and a file management server for storing original contents.

摘要翻译： 提供了一种用于内容传送系统的聚类设备和方法。 集群装置包括：本地服务器，用于通过连接到集群来执行作为提供流服务的专用服务器的操作; 以及用于存储原始内容的文件管理服务器。

公开(公告)号：US20050124128A1

公开(公告)日：2005-06-09

申请号：US11008524

申请日：2004-12-08

申请人： Hag Kim

发明人： Hag Kim

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28044 ,  H01L29/4941 ,  H01L29/6656 ,  H01L29/7833

摘要： Methods of forming a silicide layer with small grain boundary size on a source/drain region of semiconductor device are disclosed. A disclosed method comprises forming a gate insulating layer and a gate electrode on an active region of a semiconductor substrate; forming spacers on the sidewalls of the gate electrode; implanting impurity ions for a source/drain region at a high concentration by using the gate electrode and the spacers as an ion implantation mask; depositing an interlayer dielectric layer over the semiconductor substrate including the gate electrode and the spacers; forming contact holes through the interlayer dielectric layer; depositing a barrier metal layer for silicide layers along the top surface of the interlayer dielectric layer and along the sidewalls and the bottoms of the contact holes; and performing a thermal treatment process to complete a source/drain region in the active region and form silicide layers on the source/drain region and the gate electrode.

摘要翻译： 公开了在半导体器件的源极/漏极区域上形成具有小晶界尺寸的硅化物层的方法。 所公开的方法包括在半导体衬底的有源区上形成栅极绝缘层和栅电极; 在栅电极的侧壁上形成间隔物; 通过使用栅电极和间隔物作为离子注入掩模，将高浓度的源/漏区注入杂质离子; 在包括所述栅电极和所述间隔物的所述半导体衬底之上沉积层间电介质层; 形成穿过所述层间介电层的接触孔; 沿着层间电介质层的顶表面并沿着接触孔的侧壁和底部沉积用于硅化物层的阻挡金属层; 并进行热处理工艺以完成有源区中的源/漏区，并在源/漏区和栅电极上形成硅化物层。