公开(公告)号：US20080010417A1

公开(公告)日：2008-01-10

申请号：US11859955

申请日：2007-09-24

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Kevin Moore

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Kevin Moore

IPC分类号： G06F12/00

CPC分类号： G06F12/0808 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0822 ,  G06F12/1425 ,  G06F2212/1008

摘要： In one embodiment, a method comprises communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation; determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and resolving a conflict between the memory operation and the memory transaction.

摘要翻译： 在一个实施例中，一种方法包括响应于在存储器操作期间由第一节点中的处理器经历的陷阱而从系统中的第一节点与系统中的一个或多个其他节点进行通信，其中在处理器中用信号通知陷阱 响应于在执行存储器操作期间可访问的高速缓存中存储有高速缓存行的一个或多个许可位; 确定所述高速缓存行是作为其他节点之一的第二节点中的存储器事务的一部分，其中存储器事务包括看起来孤立地原子地执行的两个或多个存储器操作; 并解决内存操作和内存事务之间的冲突。

公开(公告)号：US20070255907A1

公开(公告)日：2007-11-01

申请号：US11413243

申请日：2006-04-28

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

IPC分类号： G06F13/28

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US20070260821A1

公开(公告)日：2007-11-08

申请号：US11417640

申请日：2006-05-04

申请人： Hakan Zeffer ,  Anders Landin ,  Erik Hagersten

发明人： Hakan Zeffer ,  Anders Landin ,  Erik Hagersten

IPC分类号： G06F12/00

CPC分类号： G06F12/0815

摘要： In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.

摘要翻译： 在一个实施例中，用于多节点计算机系统中的节点的存储器控​​制器包括逻辑和控制单元。 逻辑被配置为确定与内部控制器在内部网络互连上接收到的请求对应的地址是远程地址还是本地地址。 分配节点中的存储器的第一部分以存储远程数据的副本，并且剩余部分存储本地数据。 控制单元被配置为将写回数据写入第一部分中的位置。 回写数据对应于具有由逻辑检测到的相关联的远程地址的内部网络互连的回写请求。 控制单元被配置为确定响应于相关联的远程地址的位置和识别存储器中的第一部分的一个或多个指示符。

公开(公告)号：US08539455B2

公开(公告)日：2013-09-17

申请号：US12055996

申请日：2008-03-26

申请人： Erik Berg ,  Erik Hagersten ,  Hakan Zeffer ,  Magnus Vesterlund ,  Mats Nilsson ,  Mikael Petterson

发明人： Erik Berg ,  Erik Hagersten ,  Hakan Zeffer ,  Magnus Vesterlund ,  Mats Nilsson ,  Mikael Petterson

IPC分类号： G06F9/44 ,  G06F15/00 ,  G06F12/00

CPC分类号： G06F11/3447 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

摘要： A system, method, and computer program product that captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted. Reuse distance for one memory operation may be measured as the number of memory operations that have been performed since the memory object it accesses was last accessed. Separate call stacks leading up to the same memory operation are identified and statistics are separated for the different call stacks. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered. The method includes modeling multithreaded memory systems and detecting false sharing coherence misses.

摘要翻译： 一种系统，方法和计算机程序产品，可从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的重用距离度量的性能表征数据是针对性的。 一个存储器操作的重复使用距离可以被测量为自上次访问其访问的存储器对象以来已执行的存储器操作的数量。 识别导致相同内存操作的单独的调用堆栈，并为不同的调用堆栈分隔统计信息。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。 涵盖了评估缓存利用率和并行执行的方法。 该方法包括建模多线程内存系统并检测虚假共享连贯性错误。

公开(公告)号：US20090055594A1

公开(公告)日：2009-02-26

申请号：US11806997

申请日：2007-06-05

申请人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

发明人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

IPC分类号： G06F12/12

CPC分类号： G06F11/3644 ,  G06F11/3447 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

摘要： A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations.

摘要翻译： 系统，方法和计算机程序产品从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的复用距离度量的性能表征数据被定义为两次访问同一数据块之间的存储器引用的总数。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。

公开(公告)号：US08443341B2

公开(公告)日：2013-05-14

申请号：US11938247

申请日：2007-11-09

申请人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

发明人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

IPC分类号： G06F9/44

CPC分类号： G06F11/3616 ,  G06F12/0802

摘要： A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.

摘要翻译： 系统，方法和计算机程序产品从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的复用距离度量的性能表征数据被定义为两次访问同一数据块之间的存储器引用的总数。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。 涵盖了评估缓存利用率和并行执行的方法。

公开(公告)号：US20080244533A1

公开(公告)日：2008-10-02

申请号：US12055996

申请日：2008-03-26

申请人： Erik Berg ,  Erik Hagersten ,  Hakan Zeffer ,  Magnus Vesterlund ,  Mats Nilsson ,  Mikael Petterson

发明人： Erik Berg ,  Erik Hagersten ,  Hakan Zeffer ,  Magnus Vesterlund ,  Mats Nilsson ,  Mikael Petterson

IPC分类号： G06F9/44

CPC分类号： G06F11/3447 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

摘要： A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.

摘要翻译： 系统，方法和计算机程序产品从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的复用距离度量的性能表征数据被定义为两次访问同一数据块之间的存储器引用的总数。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。 涵盖了评估缓存利用率和并行执行的方法。

公开(公告)号：US08141058B2

公开(公告)日：2012-03-20

申请号：US11806997

申请日：2007-06-05

申请人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

发明人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F11/3644 ,  G06F11/3447 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

摘要： A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations.

摘要翻译： 系统，方法和计算机程序产品从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的复用距离度量的性能表征数据被定义为两次访问同一数据块之间的存储器引用的总数。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。

公开(公告)号：US20090125465A1

公开(公告)日：2009-05-14

申请号：US11938247

申请日：2007-11-09

申请人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

发明人： Erik Berg ,  Erik Hagersten ,  Mats Nilsson ,  Mikael Petterson ,  Magnus Vesterlund ,  Hakan Zeffer

IPC分类号： G06F15/18

CPC分类号： G06F11/3616 ,  G06F12/0802

摘要： A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.

摘要翻译： 系统，方法和计算机程序产品从执行程序中捕获性能特征数据，并根据该数据对系统性能进行建模。 基于容易捕获的复用距离度量的性能表征数据被定义为两次访问同一数据块之间的存储器引用的总数。 描述有效捕获这种度量的方法。 这些数据可以被简化为易于解释的性能指标，例如与具有LRU替换的缓存和随机替换策略相关联的性能数据以及完全关联以及有限关联缓存组织。 涵盖了评估缓存利用率和并行执行的方法。

公开(公告)号：US20070255908A1

公开(公告)日：2007-11-01

申请号：US11413244

申请日：2006-04-28

申请人： Hakan Zeffer ,  Erik Hagersten

发明人： Hakan Zeffer ,  Erik Hagersten

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F12/0837 ,  G06F2212/507

摘要： In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

摘要翻译： 在一个实施例中，用于多节点计算机系统的节点包括被配置为存储节点的本地存储器中的相干单元的相干状态的相干目录和被配置为接收对所请求的相干单元的一致性请求的相干控制器。 所请求的相干单元被包括在包括至少两个相干单元的存储器区域中，并且相干控制器被配置为响应于相干请求从相干目录读取与两个或更多个相干单元相对应的相干状态。 两个或更多个相干单元被包括在先前访问的存储器区域中，并且相干控制器被配置为响应于先前访问的存储器区域中的相干状态来向所请求的相干单元提供预测相干状态。