公开(公告)号：US20060040065A1

公开(公告)日：2006-02-23

申请号：US10923057

申请日：2004-08-19

申请人： Han-Chang Shih ,  Jian-Hong Lin ,  Wei-Jen Hsieh ,  Yi-Ying Tsai ,  Uei-Shin Chen

发明人： Han-Chang Shih ,  Jian-Hong Lin ,  Wei-Jen Hsieh ,  Yi-Ying Tsai ,  Uei-Shin Chen

IPC分类号： C23C14/00 ,  H01L21/4763

CPC分类号： C23C14/48 ,  C23C14/046 ,  C23C18/1879 ,  C23C18/38 ,  H01J37/32412 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76874

摘要： A method for surface activation on the metallization of electronic devices is provided. It uses plasma-immersion ion implantation and electroless plating to implant the seeds onto the diffusion barrier layer as catalyst for the electroless Cu plating to accomplish the ULSI interconnect metallization. It achieves electroless Cu plating in the deep 100 nm scaled line-width ULSI interconnect metallization by the Pd plasma implantation catalytic treatment. The method can fill the 100 nm line-width vias and trenches for gaining high quality electroless plated metal interconnects, and substitute for the traditional wet activation by SnCl2 and PdCl2 solution. For the plasma implanted seeds and electroless copper techniques, good Cu step coverage and gap-filling capability are observed in the trench and via metallization process with high adhesive strength. After thermal treatment, no obvious interfacial diffusion induced electric failure is found in the interface of the Cu/(implanted Pd)/TaN/FSG assembly. Good electric and interfacial structure reliability are observed in the process, too.

摘要翻译： 提供了一种用于电子设备的金属化表面活化的方法。 它使用等离子体浸没离子注入和无电镀来将种子植入到扩散阻挡层上，作为化学镀铜的催化剂，以实现ULSI互连金属化。 它通过Pd等离子体注入催化处理在深度为100nm的线宽ULSI互连金属化中实现无电镀铜。 该方法可以填充100nm的线宽通孔和沟槽，以获得高质量的无电镀金属互连，并且替代传统的通过SnCl 2 2和PdCl 2 2溶液的湿活化 。 对于等离子体植入种子和无电铜技术，在沟槽和通过金属化过程中观察到良好的Cu台阶覆盖和间隙填充能力，具有高的粘合强度。 热处理后，在Cu /（注入Pd）/ TaN / FSG组件的界面处没有发现明显的界面扩散引起的电气故障。 在此过程中也观察到良好的电气和界面结构的可靠性。

公开(公告)号：US08755000B2

公开(公告)日：2014-06-17

申请号：US13471425

申请日：2012-05-14

申请人： Jian-Hong Lin

发明人： Jian-Hong Lin

IPC分类号： G02F1/13 ,  G02F1/1333 ,  G02F1/1343

CPC分类号： G02F1/1345 ,  G02F1/136259 ,  G02F2001/136272

摘要： A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.

摘要翻译： 一种显示面板，包括第一基板，第二基板和液晶层。 第一衬底包括与显示区域相邻的显示区域和外围电路区域，并且第一衬底包括像素阵列，多个测试短路条和多条电线。 像素阵列设置在显示区域中。 测试短路棒设置在外围电路区域中。 电线布置在外围电路区域中并与像素阵列电连接。 此外，至少一根线和一个测试短路棒分别共享用于彼此连接并形成公共痕迹的部分。 另外，第二基板与第一基板相对设置。 液晶层设置在第一基板和第二基板之间。

公开(公告)号：US20120205206A1

公开(公告)日：2012-08-16

申请号：US13342922

申请日：2012-01-03

申请人： Jian-Yu Chen ,  Ming-Liang Wong ,  Chih-Ming Yu ,  Wun-Ya Gao ,  Jian-Hong Lin

发明人： Jian-Yu Chen ,  Ming-Liang Wong ,  Chih-Ming Yu ,  Wun-Ya Gao ,  Jian-Hong Lin

IPC分类号： F16F9/08

CPC分类号： F16F9/096

摘要： A hydraulic buffer device includes a first chamber, a second chamber, and a buffering space disposed under the first and second chambers, an air bladder disposed in the buffering space, an oil chamber disposed above the first and second chambers and divided by a piston into upper and lower chamber portions, and an annular passage disposed around the oil chamber. When the piston is moved downwardly within the oil chamber, the hydraulic oil flows from the lower chamber portion into the buffering space via the first chamber to contract the air bladder so that, upon expansion of the air bladder, air pressure in the air bladder pushes the hydraulic oil to flow from the buffering space into the upper chamber portion via the second chamber and the annular passage.

摘要翻译： 液压缓冲装置包括第一室，第二室和设置在第一和第二室下方的缓冲空间，设置在缓冲空间中的空气囊，设置在第一和第二室上方并由活塞分隔的油室 上室和下室部分以及设置在油室周围的环形通道。 当活塞在油室内向下移动时，液压油经由第一腔室从下室部分流入缓冲空间，以使气囊收缩，使得当气囊膨胀时，空气囊中的空气压力推动 所述液压油经由所述第二室和所述环形通道从所述缓冲空间流入所述上室部。

公开(公告)号：US20110069806A1

公开(公告)日：2011-03-24

申请号：US12565226

申请日：2009-09-23

申请人： Yi-Suei Liao ,  Jian-Hong Lin

发明人： Yi-Suei Liao ,  Jian-Hong Lin

IPC分类号： G11C19/00 ,  H03L5/00

CPC分类号： G11C19/28 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184

摘要： The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.

摘要翻译： 本发明涉及一种下拉控制电路和使用它的移位寄存器。 在一个实施例中，下拉控制电路包括释放电路和彼此电耦合的四个晶体管T4，T5，T6和T7。 释放电路适于使晶体管T5交替地导通和截止，从而大大降低其上的应力，提高可靠性并延长移位寄存器的寿命。

公开(公告)号：US20100327456A1

公开(公告)日：2010-12-30

申请号：US12879770

申请日：2010-09-10

申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US20100014030A1

公开(公告)日：2010-01-21

申请号：US12369748

申请日：2009-02-12

申请人： Jian-Hong Lin

发明人： Jian-Hong Lin

IPC分类号： G02F1/13357 ,  G02F1/1333

CPC分类号： G02F1/1345 ,  G02F1/136259 ,  G02F2001/136272

摘要： An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace.

摘要翻译： 提供了具有与显示区域相邻的显示区域和外围电路区域的阵列基板。 阵列基板包括像素阵列，多个测试短路棒和多根线。 像素阵列设置在显示区域中。 测试短路棒设置在外围电路区域中。 与像素阵列电连接的布线设置在外围电路区域中。 特别地，至少一根电线和测试短路棒共享用于彼此连接的部件，并且该部件形成共同的轨迹。

公开(公告)号：US20120050658A1

公开(公告)日：2012-03-01

申请号：US13005538

申请日：2011-01-13

申请人： Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

发明人： Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

IPC分类号： G02F1/1343

CPC分类号： G02F1/136259 ,  G02F2001/13606 ,  G02F2001/136263 ,  G02F2001/136272

摘要： A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.

摘要翻译： 显示面板包括有源器件阵列衬底，相对衬底和液晶层。 有源器件阵列衬底包括衬底，并且还包括像素阵列，信号线以及全部设置在衬底上的第一和第二修复线。 信号线电连接像素阵列。 第一修复线包括分别位于像素阵列的第一和第二侧上的第一和第二线段。 第一侧基本垂直于第二侧。 第一和第二线段电连接。 第二修复线包括分别位于像素阵列的第三和第二侧上的第三和第四线段。 第三侧基本上平行于第一侧。 第四和第三线段电连接。 有源器件阵列衬底上方的相对衬底不覆盖第一和第三线段。

公开(公告)号：US20110108945A1

公开(公告)日：2011-05-12

申请号：US13007927

申请日：2011-01-17

申请人： Chien-Jung Wang ,  Jian-Hong Lin

发明人： Chien-Jung Wang ,  Jian-Hong Lin

IPC分类号： H01L27/04

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

摘要翻译： 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并且具有面向所述开口的部分。

公开(公告)号：US07816256B2

公开(公告)日：2010-10-19

申请号：US11487741

申请日：2006-07-17

申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US20090058434A1

公开(公告)日：2009-03-05

申请号：US11849836

申请日：2007-09-04

申请人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

发明人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

IPC分类号： G01R27/00

CPC分类号： G01R31/2858 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

摘要翻译： 提供了一种用于测量互连性质的方法。 该方法包括以下步骤。 提供多个互连测试图案。 形成多个互连测试图案并联连接的焊盘。 至少一个电阻器形成在所述多个互连测试图案中的至少一个与所述焊盘之间。 通过对焊盘施加电流，电压和/或机械应力来测量多个互连测试图案的性质。