公开(公告)号：US20090242883A1

公开(公告)日：2009-10-01

申请号：US12149858

申请日：2008-05-09

申请人： Han-Tu Lin ,  Chih-Chun Yang ,  Chin-Yueh Liao ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chih-Chun Yang ,  Chin-Yueh Liao ,  Chien-Hung Chen

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L29/42384 ,  H01L27/1218 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78603

摘要： A thin film transistor, an active array substrate having the same and methods for manufacturing the same are provided. The thin film transistor includes a base having a concave; a gate disposed in the concave; a gate insulator covering the gate and a portion of the gate insulator is in the concave; a channel layer disposed on the gate insulator; and a source and a drain are disposed on the channel layer and located in response to two sides of the gate.

摘要翻译： 提供薄膜晶体管，具有该薄膜晶体管的有源阵列基板及其制造方法。 薄膜晶体管包括具有凹面的基底; 设置在凹面中的门; 覆盖栅极的栅极绝缘体和栅极绝缘体的一部分在凹部中; 设置在栅极绝缘体上的沟道层; 并且源极和漏极设置在沟道层上并且响应于栅极的两侧而定位。

公开(公告)号：US20100320466A1

公开(公告)日：2010-12-23

申请号：US12560428

申请日：2009-09-16

申请人： Chien-Hung Chen ,  Lih-Hsiung Chan ,  Chin-Yueh Liao ,  Hsien-Kai Tseng

发明人： Chien-Hung Chen ,  Lih-Hsiung Chan ,  Chin-Yueh Liao ,  Hsien-Kai Tseng

IPC分类号： H01L33/00 ,  H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.

摘要翻译： 提供薄膜晶体管阵列基板及其制造方法。 在制造方法中，在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。 然后在衬底上形成具有多个开口的图案化栅极绝缘层，以覆盖第一图案化导电层的至少一部分，并且在开口中形成多个电介质图案。 在图案化的栅极绝缘层上形成多个半导体图案。 在半导体图案，图案化栅极绝缘层和电介质图案上形成第二图案化导电层。 在半导体图案，图案化栅绝缘层和电介质图案上形成钝化层。 在钝化层上形成多个像素电极。

公开(公告)号：US08314423B2

公开(公告)日：2012-11-20

申请号：US12560428

申请日：2009-09-16

申请人： Chien-Hung Chen ,  Lih-Hsiung Chan ,  Chin-Yueh Liao ,  Hsien-Kai Tseng

发明人： Chien-Hung Chen ,  Lih-Hsiung Chan ,  Chin-Yueh Liao ,  Hsien-Kai Tseng

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.

摘要翻译： 提供薄膜晶体管阵列基板及其制造方法。 在制造方法中，在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。 然后在衬底上形成具有多个开口的图案化栅极绝缘层，以覆盖第一图案化导电层的至少一部分，并且在开口中形成多个电介质图案。 在图案化的栅极绝缘层上形成多个半导体图案。 在半导体图案，图案化栅极绝缘层和电介质图案上形成第二图案化导电层。 在半导体图案，图案化栅绝缘层和电介质图案上形成钝化层。 在钝化层上形成多个像素电极。

公开(公告)号：US20110117707A1

公开(公告)日：2011-05-19

申请号：US13013887

申请日：2011-01-26

申请人： Han-Tu Lin ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chien-Hung Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

摘要翻译： 提供了一种用于制造像素结构的方法。 首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。 接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。 然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。

公开(公告)号：US20100051954A1

公开(公告)日：2010-03-04

申请号：US12591019

申请日：2009-11-05

申请人： Han-Tu Lin ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chien-Hung Chen

IPC分类号： H01L33/00 ,  H01L31/0224

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

摘要翻译： 提供了一种用于制造像素结构的方法。 首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。 接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。 然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。

公开(公告)号：US20090101902A1

公开(公告)日：2009-04-23

申请号：US12076297

申请日：2008-03-17

申请人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

发明人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.

摘要翻译： 提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。 在衬底上有序地形成透明导电层和第一金属层。 在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。 接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。 然后，分别形成第二金属层和第一光致抗蚀剂层。 之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。 最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

公开(公告)号：US20120115265A1

公开(公告)日：2012-05-10

申请号：US13354618

申请日：2012-01-20

申请人： Han-Tu LIN ,  Chien-Hung Chen ,  Shiun-Chang Jan

发明人： Han-Tu LIN ,  Chien-Hung Chen ,  Shiun-Chang Jan

IPC分类号： H01L31/18

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.

摘要翻译： 提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。 在衬底上有序地形成透明导电层和第一金属层。 在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。 接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。 然后，分别形成第二金属层和第一光致抗蚀剂层。 之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。 最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

公开(公告)号：US08143624B2

公开(公告)日：2012-03-27

申请号：US12076297

申请日：2008-03-17

申请人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

发明人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

IPC分类号： H01L27/14

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.

摘要翻译： 提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。 在衬底上有序地形成透明导电层和第一金属层。 在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。 接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。 然后，分别形成第二金属层和第一光致抗蚀剂层。 之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。 最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

公开(公告)号：US08383466B2

公开(公告)日：2013-02-26

申请号：US13354618

申请日：2012-01-20

申请人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

发明人： Han-Tu Lin ,  Chien-Hung Chen ,  Shiun-Chang Jan

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.

公开(公告)号：US20090108260A1

公开(公告)日：2009-04-30

申请号：US12076681

申请日：2008-03-21

申请人： Han-Tu Lin ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chien-Hung Chen

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

摘要翻译： 提供了一种用于制造像素结构的方法。 首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。 接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。 然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。