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公开(公告)号：US07635908B2
公开(公告)日：2009-12-22
申请号：US11652157
申请日：2007-01-11
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译： 本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极 层。 使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极 位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。 这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。
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公开(公告)号：US20090073633A1
公开(公告)日：2009-03-19
申请号：US11856775
申请日：2007-09-18
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。
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公开(公告)号：US20090072411A1
公开(公告)日：2009-03-19
申请号：US11855170
申请日：2007-09-14
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧 所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。
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公开(公告)号：US20090072388A1
公开(公告)日：2009-03-19
申请号：US11856089
申请日：2007-09-17
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。
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公开(公告)号：US07986023B2
公开(公告)日：2011-07-26
申请号：US11856089
申请日：2007-09-17
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。
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公开(公告)号：US07816792B2
公开(公告)日：2010-10-19
申请号：US11855170
申请日：2007-09-14
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧 所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。
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公开(公告)号：US20090236647A1
公开(公告)日：2009-09-24
申请号：US12050192
申请日：2008-03-18
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
CPC分类号： H01L23/5389 , H01L23/49861 , H01L23/50 , H01L23/642 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/40 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00
摘要： An embodiment of the invention is a semiconductor structure, comprising: a semiconductor chip at least partially embedded within a support; and a capacitor disposed outside the lateral boundary of the chip, the capacitor electrically coupled to the chip.
摘要翻译： 本发明的实施例是一种半导体结构，包括：半导体芯片，其至少部分地嵌入在支撑体内; 以及设置在所述芯片的横向边界外侧的电容器，所述电容器电耦合到所述芯片。
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公开(公告)号：US20070155090A1
公开(公告)日：2007-07-05
申请号：US11652157
申请日：2007-01-11
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译： 本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极 层。 使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极 位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。 这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。
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公开(公告)号：US07915132B2
公开(公告)日：2011-03-29
申请号：US12562460
申请日：2009-09-18
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译： 本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极 层。 使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极 位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。 这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。
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公开(公告)号：US07777300B2
公开(公告)日：2010-08-17
申请号：US11856775
申请日：2007-09-18
IPC分类号： H01L23/52
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。
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