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公开(公告)号：US07777300B2
公开(公告)日：2010-08-17
申请号：US11856775
申请日：2007-09-18
IPC分类号： H01L23/52
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。
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公开(公告)号：US20090073633A1
公开(公告)日：2009-03-19
申请号：US11856775
申请日：2007-09-18
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。
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公开(公告)号：US07986023B2
公开(公告)日：2011-07-26
申请号：US11856089
申请日：2007-09-17
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。
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公开(公告)号：US07816792B2
公开(公告)日：2010-10-19
申请号：US11855170
申请日：2007-09-14
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧 所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。
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公开(公告)号：US20090072411A1
公开(公告)日：2009-03-19
申请号：US11855170
申请日：2007-09-14
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧 所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。
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公开(公告)号：US20090072388A1
公开(公告)日：2009-03-19
申请号：US11856089
申请日：2007-09-17
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。
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公开(公告)号：US08106497B2
公开(公告)日：2012-01-31
申请号：US11622691
申请日：2007-01-12
申请人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
发明人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
IPC分类号： H01L21/02
CPC分类号： H01L25/0657 , H01L23/3675 , H01L23/373 , H01L23/3733 , H01L24/48 , H01L2224/05554 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73253 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01068 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.
摘要翻译： 公开了一种具有半导体芯片堆叠的半导体模块及其制造方法。 在一个实施例中，具有各向异性导热颗粒的导热层布置在半导体芯片之间。 各向异性导热颗粒在相对于层或膜垂直的方向上比在层或膜的方向上具有较低的热导率。
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公开(公告)号：US08587110B2
公开(公告)日：2013-11-19
申请号：US13332414
申请日：2011-12-21
申请人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
发明人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
IPC分类号： H01L21/02
CPC分类号： H01L25/0657 , H01L23/3675 , H01L23/373 , H01L23/3733 , H01L24/48 , H01L2224/05554 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73253 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01068 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.
摘要翻译： 公开了一种具有半导体芯片堆叠的半导体模块及其制造方法。 在一个实施例中，具有各向异性导热颗粒的导热层布置在半导体芯片之间。 各向异性导热颗粒在相对于层或膜垂直的方向上比在层或膜的方向上具有较低的热导率。
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公开(公告)号：US20120104592A1
公开(公告)日：2012-05-03
申请号：US13332414
申请日：2011-12-21
申请人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
发明人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
IPC分类号： H01L23/367 , H01L21/52 , H01L25/00 , B82Y99/00
CPC分类号： H01L25/0657 , H01L23/3675 , H01L23/373 , H01L23/3733 , H01L24/48 , H01L2224/05554 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73253 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01068 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.
摘要翻译： 公开了一种具有半导体芯片堆叠的半导体模块及其制造方法。 在一个实施例中，具有各向异性导热颗粒的导热层布置在半导体芯片之间。 各向异性导热颗粒在相对于层或膜垂直的方向上比在层或膜的方向上具有较低的热导率。
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公开(公告)号：US20070176277A1
公开(公告)日：2007-08-02
申请号：US11622691
申请日：2007-01-12
申请人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
发明人： Markus Brunnbauer , Markus Fink , Hans-Gerd Jetten
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3675 , H01L23/373 , H01L23/3733 , H01L24/48 , H01L2224/05554 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73253 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01068 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.
摘要翻译： 公开了一种具有半导体芯片堆叠的半导体模块及其制造方法。 在一个实施例中，具有各向异性导热颗粒的导热层布置在半导体芯片之间。 各向异性导热颗粒在相对于层或膜垂直的方向上比在层或膜的方向上具有较低的热导率。
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