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    Method of forming tensile stress films for NFET performance enhancement
    1.
    发明申请
    Method of forming tensile stress films for NFET performance enhancement 审中-公开
    形成用于NFET性能提高的拉伸应力膜的方法

    公开(公告)号：US20080138983A1

    公开(公告)日：2008-06-12

    申请号：US11634303

    申请日：2006-12-06

    申请人： Hao-Ming Lien ,  Jim Cy Huang ,  Donald Y. Chao ,  Ling-Yen Yeh ,  Hun-Jan Tao

    发明人： Hao-Ming Lien ,  Jim Cy Huang ,  Donald Y. Chao ,  Ling-Yen Yeh ,  Hun-Jan Tao

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76832 ,  H01L21/2686 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A method of forming tensile stress films for NFET Performance enhancement, comprising the steps of: (a) providing a semiconductor substrate having a gate structure patterned thereon; (b) performing a deposition process to form a first dielectric film overlying the semiconductor substrate and covering the gate structure; (c) performing a curing process on the first dielectric film; (d) successively repeating the step (b) of deposition process and the step (c) of curing process at least once to form at least one second dielectric film on the first dielectric film until the total thickness of the first dielectric film and the at least one second dielectric film reaches a target thickness.

    摘要翻译： 一种形成用于NFET性能增强的拉伸应力膜的方法，包括以下步骤：（a）提供在其上图案化的栅极结构的半导体衬底; （b）进行沉积工艺以形成覆盖半导体衬底并覆盖栅极结构的第一电介质膜; （c）对所述第一电介质膜进行固化处理; （d）连续重复沉积处理步骤（b）和固化过程的步骤（c）至少一次，以在第一介电膜上形成至少一个第二电介质膜，直到第一介电膜和第 至少一个第二介电膜达到目标厚度。

    Hybrid STI stressor with selective re-oxidation anneal
    2.
    发明授权
    Hybrid STI stressor with selective re-oxidation anneal 有权
    混合STI应力选择性再氧化退火

    公开(公告)号：US07276417B2

    公开(公告)日：2007-10-02

    申请号：US11320221

    申请日：2005-12-28

    申请人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

    发明人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/7846

    摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

    摘要翻译： 提供了一种在半导体衬底中形成应力源的方法。 该方法包括提供包括第一器件区域和第二器件区域的半导体衬底，在第一和第二器件区域中形成具有高收缩介电材料的浅沟槽隔离（STI）区域，其中STI区域限定第一有源区域 在所述第一器件区域和所述第二器件区域中的第二有源区域中，在所述STI区域和所述第一器件区域中的所述第一有源区域上形成绝缘掩模，其中所述绝缘掩模不在所述第二器件区域上延伸，并执行 对半导体衬底进行应力调谐处理。 第一活性区和第二活性区分别具有拉伸应力和压应力。 分别在第一和第二有源区上形成NMOS和PMOS器件。

    Hybrid STI stressor with selective re-oxidation anneal
    3.
    发明申请
    Hybrid STI stressor with selective re-oxidation anneal 有权

    公开(公告)号：US20070148881A1

    公开(公告)日：2007-06-28

    申请号：US11320221

    申请日：2005-12-28

    申请人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

    发明人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/7846

    摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

    Method for operating nonvolatitle memory array
    5.
    发明授权
    Method for operating nonvolatitle memory array 有权
    用于操作非标量存储器阵列的方法

    公开(公告)号：US07852673B2

    公开(公告)日：2010-12-14

    申请号：US12561849

    申请日：2009-09-17

    申请人： Hao-Ming Lien ,  Ming-Hsiu Lee

    发明人： Hao-Ming Lien ,  Ming-Hsiu Lee

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

    摘要： A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.

    摘要翻译： 一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。 该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

    METHOD OF PROGRAMMING NON-VOLATILE MEMORY
    7.
    发明申请
    METHOD OF PROGRAMMING NON-VOLATILE MEMORY 有权
    编程非易失性存储器的方法

    公开(公告)号：US20080056009A1

    公开(公告)日：2008-03-06

    申请号：US11930132

    申请日：2007-10-31

    申请人： Cheng-Hsing Hsu ,  Hao-Ming Lien

    发明人： Cheng-Hsing Hsu ,  Hao-Ming Lien

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： H01L29/7923 ,  G11C16/12 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66833

    摘要： A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.

    摘要翻译： 提供具有栅极结构的非易失性存储器，一对存储单元和两个辅助栅极。 栅极结构设置在基板上。 存储单元设置在栅极结构的侧壁上。 辅助闸门设置在闸门结构的相应侧面上并且与储存单元相邻。 每个辅助门在两个相邻的存储单元之间共享。 栅极结构，存储单元和辅助栅极彼此电隔离。

    Non-volatile memory
    8.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号：US07307882B2

    公开(公告)日：2007-12-11

    申请号：US11160561

    申请日：2005-06-29

    申请人： Cheng-Hsing Hsu ,  Hao-Ming Lien

    发明人： Cheng-Hsing Hsu ,  Hao-Ming Lien

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： H01L29/7923 ,  G11C16/12 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66833

    摘要： A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.

    摘要翻译： 提供具有栅极结构的非易失性存储器，一对存储单元和两个辅助栅极。 栅极结构设置在基板上。 存储单元设置在栅极结构的侧壁上。 辅助闸门设置在闸门结构的相应侧面上并且与储存单元相邻。 每个辅助门在两个相邻的存储单元之间共享。 栅极结构，存储单元和辅助栅极彼此电隔离。

    Method of semiconductor integrated circuit fabrication
    9.
    发明授权
    Method of semiconductor integrated circuit fabrication 有权
    半导体集成电路制造方法

    公开(公告)号：US08735252B2

    公开(公告)日：2014-05-27

    申请号：US13490635

    申请日：2012-06-07

    申请人： Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

    发明人： Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76224 ,  H01L29/66795

    摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

    摘要翻译： 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

    Method for fabricating an isolation structure
    10.
    发明授权
    Method for fabricating an isolation structure 有权
    隔离结构的制造方法

    公开(公告)号：US08404561B2

    公开(公告)日：2013-03-26

    申请号：US12774219

    申请日：2010-05-05

    申请人： Tze-Liang Lee ,  Pei-Ren Jeng ,  Chu-Yun Fu ,  Chyi Shyuan Chern ,  Jui-Hei Huang ,  Chih-Tang Peng ,  Hao-Ming Lien

    发明人： Tze-Liang Lee ,  Pei-Ren Jeng ,  Chu-Yun Fu ,  Chyi Shyuan Chern ,  Jui-Hei Huang ,  Chih-Tang Peng ,  Hao-Ming Lien

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/76232

    摘要： The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.

    摘要翻译： 本发明涉及集成电路制造，更具体地说涉及具有几乎没有空隙的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：提供衬底; 在衬底中形成沟槽; 用第一氧化硅部分地填充沟槽; 将第一氧化硅的表面暴露于包含NH 3和含氟化合物的蒸汽混合物中; 将基板加热至100℃至200℃的温度; 并用第二氧化硅填充沟槽，由此所制成的隔离结构几乎没有空隙。