公开(公告)号：US08450161B2

公开(公告)日：2013-05-28

申请号：US13465551

申请日：2012-05-07

申请人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20100044803A1

公开(公告)日：2010-02-25

申请号：US12389535

申请日：2009-02-20

申请人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US5638803A

公开(公告)日：1997-06-17

申请号：US516878

申请日：1995-08-18

申请人： Chi-hsin Chang

发明人： Chi-hsin Chang

IPC分类号： F02D33/00 ,  F02M37/00 ,  F02M25/07

CPC分类号： F02D33/006 ,  F02M37/0023 ,  F02M37/007 ,  Y10S123/03

摘要： The present invention relates to a fueling control device for a remote-control model to prevent fuel oil overflow and to stop fueling automatically by sensing fuel oil delivery pressure. The device has a check valve, a pump and a control device with an electronic control consisting of a DC power supply circuit, a voltage regulation circuit, a switch type voltage regulation circuit, a control key, a CPU, a differential current inspection circuit, a motor circuit, and a motor driven pump. The check valve is connected between the fuel oil tank and an air conduit connected to a muffler. The pump is connected between a fuel oil drum, and a fuel oil delivery tube for pumping fuel oil from the fuel oil drum into the fuel oil tank. When the fuel oil tank is filled, overflow fuel oil causes closure of the check valve to cause a sudden rise of fuel oil delivery pressure. The rising load on the motor is transmitted to the control device to cause the pump to stop running.

摘要翻译： 本发明涉及一种用于遥控模型的加油控制装置，以防止燃料油溢出并通过感测燃油输送压力自动停止加油。 该装置具有止回阀，泵和具有由直流电源电路，电压调节电路，开关型电压调节电路，控制键，CPU，差动电流检测电路组成的电子控制的控制装置， 马达回路，马达驱动泵。 止回阀连接在燃油箱和连接到消声器的空气管道之间。 泵连接在燃料油桶和燃料油输送管之间，用于将燃料油从燃料油桶泵送到燃料油箱中。 当燃油箱填满时，溢油燃油导致止回阀关闭，导致燃油输送压力突然上升。 电机上升的负载被传送到控制装置，使泵停止运行。

公开(公告)号：US20140009999A1

公开(公告)日：2014-01-09

申请号：US13665941

申请日：2012-11-01

申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

摘要翻译： 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

公开(公告)号：US08193586B2

公开(公告)日：2012-06-05

申请号：US12389535

申请日：2009-02-20

申请人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

发明人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

IPC分类号： H01L21/02 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08854897B2

公开(公告)日：2014-10-07

申请号：US13665941

申请日：2012-11-01

申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC分类号： G11C7/10

CPC分类号： G11C11/413

摘要： A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

摘要翻译： 静态随机存取存储装置和位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

申请人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。