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公开(公告)号：US09152517B2
公开(公告)日：2015-10-06
申请号：US13091879
申请日：2011-04-21
申请人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
发明人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
CPC分类号： G06F11/24 , G01R31/2877 , G06F1/206 , G06F1/3203
摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.
摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。
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公开(公告)号：US20120272100A1
公开(公告)日：2012-10-25
申请号：US13091879
申请日：2011-04-21
申请人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
发明人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
IPC分类号： G06F11/07
CPC分类号： G06F11/24 , G01R31/2877 , G06F1/206 , G06F1/3203
摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.
摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。
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公开(公告)号：US07265561B2
公开(公告)日：2007-09-04
申请号：US10605449
申请日：2003-09-30
IPC分类号： G01R31/02
CPC分类号： G01R31/2879 , G01R31/2863
摘要： According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.
摘要翻译： 根据本发明，提供了一种在工具燃烧中控制至少一个I / C装置的燃烧的方法。 对于大功率设备，该工具具有一个定位成与被烧入的每个设备接触的散热器，并且具有用于安装每个要被燃烧的设备的插座和用于在每个设备中提供电流的电源。 该方法包括以下步骤：连续监测从电流，电压，功率和温度组中选出的至少一个过程参数，以及改变电压以将至少一个参数保持在给定值或低于给定值。 另外，提供了一种在没有散热片的低功率设备中燃烧的技术。 本发明还考虑了用于执行上述方法的工具。
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公开(公告)号：US06275051B1
公开(公告)日：2001-08-14
申请号：US09240121
申请日：1999-01-29
申请人： Thomas W. Bachelder , Dennis R. Barringer , Dennis R. Conti , James M. Crafts , David L. Gardell , Paul M. Gaschke , Mark R. Laforce , Charles H. Perry , Roger R. Schmidt , Joseph J. Van Horn , Wade H. White
发明人： Thomas W. Bachelder , Dennis R. Barringer , Dennis R. Conti , James M. Crafts , David L. Gardell , Paul M. Gaschke , Mark R. Laforce , Charles H. Perry , Roger R. Schmidt , Joseph J. Van Horn , Wade H. White
IPC分类号： G01R1073
CPC分类号： G01R31/2863
摘要： An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.
摘要翻译： 用于在产品晶片上同时测试或燃烧大量集成电路芯片的装置包括安装在第一板上的探针和安装在第二板上的测试器芯片，连接两个板的电连接器。 测试器芯片用于向产品芯片分配电力或用于测试产品芯片。 其所附接的探针和薄膜布线被个性化以用于被探测的特定晶片的焊盘覆盖区。 第一板和第二板的基座对于产品系列中的所有晶片都保持不变。 使用两个电路板提供了测试器芯片在燃烧期间保持在比产品芯片基本上更低的温度，以延长测试器芯片的寿命。 间隙可以用作板之间的绝热，并将间隙密封并抽真空以进行进一步的隔热。 疏散还提供大气压力增加的接触，用于连接板和与晶片的接触。 用于平行测试芯片的探针被布置成月牙形条纹，以便与布置在区域阵列中的探针相比显着增加测试仪的吞吐量。
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5.发明授权
公开(公告)号：US4751656A
公开(公告)日：1988-06-14
申请号：US838000
申请日：1986-03-10
CPC分类号： G11C29/72
摘要： A method of assigning replacement rows and colums in a two dimensionally redundant array in which if the number of failures along a row exceeds the number of remaining redundant columns, then replacing that row with one of the redundant rows. The process is repeated in the opposite direction with the number of remaining redundant rows and columns being properly decremented. The process of reversing directions continues until the above condition is no longer satisfied.
摘要翻译： 在二维冗余阵列中分配替换行和列的方法，其中如果一行中的故障数量超过剩余冗余列的数量，则用其中一个冗余行替换该行。 该过程在相反方向重复，剩余的冗余行和列的数量被正确递减。 反转方向的过程将持续到上述条件不再满足为止。
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6.发明授权Applying parametric test patterns for high pin count ASICs on low pin count testers 失效在低引脚数测试仪上应用高引脚数ASIC的参数测试模式公开(公告)号：US06847203B1
公开(公告)日：2005-01-25
申请号：US10604230
申请日：2003-07-02
申请人： Dennis R. Conti , John Lafferty
发明人： Dennis R. Conti , John Lafferty
IPC分类号： G01R1/00 , G01R31/26 , G01R31/319
CPC分类号： G01R31/31926
摘要： Disclosed is an integrated circuit chip test apparatus that has a module test fixture having contact pads that are adapted to make contact with signal input/output pins on an integrated circuit chip being tested. An intermediate banking box is connected to the module text fixture and a tester is connected to the intermediate banking box. The tester includes at least one bank of channels there are more pins on the integrated circuit chip than there are channels in the tester. The intermediate banking box includes switches that are connected between the contact pads and the channels. The switches are adapted to selectively connect a subset of the contact pads to the channels to connect the tester to a subset of pins, thereby allowing the tester to test a portion of the integrated circuit that corresponds to the subset of pins.
摘要翻译： 公开了一种集成电路芯片测试装置，其具有具有接触焊盘的模块测试夹具，其适于与被测试的集成电路芯片上的信号输入/输出引脚接触。 中间银行盒连接到模块文本夹具，测试器连接到中间银行盒。 测试仪包括至少一组通道，集成电路芯片上有比测试仪中的通道更多的引脚。 中间银行箱包括连接在接触垫和通道之间的开关。 开关适于选择性地将接触焊盘的子集连接到通道以将测试器连接到引脚的子集，从而允许测试仪测试与引脚子集相对应的集成电路的一部分。
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