公开(公告)号：US09152517B2

公开(公告)日：2015-10-06

申请号：US13091879

申请日：2011-04-21

申请人： Harold Chase ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Andrew T. Holle ,  Adrian Patrascu ,  Jody J. Van Horn

发明人： Harold Chase ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Andrew T. Holle ,  Adrian Patrascu ,  Jody J. Van Horn

IPC分类号： G06F11/24 ,  G06F1/32 ,  G06F1/20 ,  G01R31/28

CPC分类号： G06F11/24 ,  G01R31/2877 ,  G06F1/206 ,  G06F1/3203

摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。

公开(公告)号：US20120272100A1

公开(公告)日：2012-10-25

申请号：US13091879

申请日：2011-04-21

申请人： Harold Chase ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Andrew T. Holle ,  Adrian Patrascu ,  Jody J. Van Horn

发明人： Harold Chase ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Andrew T. Holle ,  Adrian Patrascu ,  Jody J. Van Horn

IPC分类号： G06F11/07

CPC分类号： G06F11/24 ,  G01R31/2877 ,  G06F1/206 ,  G06F1/3203

摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。

公开(公告)号：US06275051B1

公开(公告)日：2001-08-14

申请号：US09240121

申请日：1999-01-29

申请人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

发明人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

IPC分类号： G01R1073

CPC分类号： G01R31/2863

摘要： An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

摘要翻译： 用于在产品晶片上同时测试或燃烧大量集成电路芯片的装置包括安装在第一板上的探针和安装在第二板上的测试器芯片，连接两个板的电连接器。 测试器芯片用于向产品芯片分配电力或用于测试产品芯片。 其所附接的探针和薄膜布线被个性化以用于被探测的特定晶片的焊盘覆盖区。 第一板和第二板的基座对于产品系列中的所有晶片都保持不变。 使用两个电路板提供了测试器芯片在燃烧期间保持在比产品芯片基本上更低的温度，以延长测试器芯片的寿命。 间隙可以用作板之间的绝热，并将间隙密封并抽真空以进行进一步的隔热。 疏散还提供大气压力增加的接触，用于连接板和与晶片的接触。 用于平行测试芯片的探针被布置成月牙形条纹，以便与布置在区域阵列中的探针相比显着增加测试仪的吞吐量。

公开(公告)号：US08734006B2

公开(公告)日：2014-05-27

申请号：US13039037

申请日：2011-03-02

申请人： James M. Crafts ,  Joseph E. Dery ,  Timothy M. Skergan ,  Timothy C. Taylor

发明人： James M. Crafts ,  Joseph E. Dery ,  Timothy M. Skergan ,  Timothy C. Taylor

IPC分类号： G01K15/00 ,  G01K7/00

CPC分类号： G01K15/005 ,  G01K7/01

摘要： A method of calibrating a thermal sensor includes setting a wafer to a control temperature. The wafer includes the thermal sensor and other chip logic. The method also includes applying power exclusively to a thermal sensor circuit, calibrating the thermal sensor, and storing a calibration result. The method also includes retrieving the calibration result upon application of power to the other chip logic.

摘要翻译： 校准热传感器的方法包括将晶片设置为控制温度。 晶片包括热传感器和其他芯片逻辑。 该方法还包括将功率专用于热传感器电路，校准热传感器以及存储校准结果。 该方法还包括在向另一个芯片逻辑施加电力时检索校准结果。