公开(公告)号：US06854041B2

公开(公告)日：2005-02-08

申请号：US10065839

申请日：2002-11-25

申请人： James J. Covino ,  Kevin G. Petrunich ,  Harold Pilo

发明人： James J. Covino ,  Kevin G. Petrunich ,  Harold Pilo

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C11/409 ,  G06F13/14

CPC分类号： G11C11/40618 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/406 ,  G11C11/409

摘要： A structure and method for performing back-to-back read and write memory operations to a same DRAM bank comprising articulating between reading data on a first bank during successive first bank read cycles and writing data to a second bank during successive second bank write cycles, cycling between reading data on the second bank during successive second bank read cycles and writing data to the first bank during successive first bank write cycles, and performing a refresh cycle on the first and second bank, wherein the first bank write cycles lag the first bank read cycles, and wherein the second bank write cycles lag the second bank read cycles. Moreover, the read and write memory operations constantly swap between the read and write cycles and between the first and second bank.

摘要翻译： 一种用于对同一DRAM组执行背靠背读和写存储器操作的结构和方法，包括在连续的第一存储体读周期期间在第一存储体上读取数据和在连续的第二存储体写周期期间将数据写入第二存储体的关系， 在连续的第二组读取周期期间在第二组上的读取数据之间循环，并且在连续的第一组写周期期间将数据写入第一组，并且在第一和第二组上执行刷新周期，其中第一组写入周期落后于第一组 读周期，并且其中第二存储体写周期滞后于第二存储体读周期。 此外，读和写存储器操作在读和写周期之间以及第一和第二存储体之间不断地交换。

公开(公告)号：US6134182A

公开(公告)日：2000-10-17

申请号：US420694

申请日：1999-10-19

申请人： Harold Pilo ,  James J. Covino

发明人： Harold Pilo ,  James J. Covino

IPC分类号： G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

摘要翻译： 提供了比较器和可变延迟电路，以在双倍数据速率（DDR）RAM器件中保持数据和回波时钟之间的跟踪。 这是通过提供与实际存储器阵列数据进行跟踪的全局数据信号（虚拟数据信号）来实现的。 将该全局数据信号与RAM时钟（CLOCK）的定时进行比较，以确定必须延迟流水线时钟（CLKRISE / CLKFALL）的两个之间的延迟时间。 结果，流水线时钟根据需要被推出，使得它们总是在阵列数据到达输出锁存器之后转换。 因此，随着周期时间的减​​少，回波时钟和数据都被相同地推出并保持其所需的跟踪。

公开(公告)号：US6038181A

公开(公告)日：2000-03-14

申请号：US136112

申请日：1998-08-18

申请人： George M. Braceras ,  James J. Covino ,  Richard E. Hee ,  Harold Pilo

发明人： George M. Braceras ,  James J. Covino ,  Richard E. Hee ,  Harold Pilo

IPC分类号： G11C29/00 ,  G01R31/30 ,  G11C7/00

CPC分类号： G01R31/30

摘要： The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.

摘要翻译： 所公开的发明提供了一种提高老化测试速度的半导体器件的电路和老化测试方法。 本发明通过在每个功率循环期间使被测设备中的每一个被测试多次（从2到32倍）来实现。 通过被测单元的这种多次循环，在电源循环期间，总测试时间缩短。 还已经发现，根据本发明测试的装置被更有效地应力并且具有比通过现有技术测试的装置更大的可靠性。 根据本发明，被测试的存储器或逻辑器件设置有相应的时钟装置，其将在每个功率循环期间通过多次（从2到32+倍）的写入和读取操作来操作被测试的每个器件。 如果在读取操作期间记录任何失败，则提供每个读取操作的数据一致性。 因此，本发明提供了一种老化测试，其更有效地将半导体器件（例如存储器或逻辑单元）应力高达32倍。本发明通过在半导体器件的周期内循环该时钟x次来利用半导体器件的内部时钟 在老化测试中每个外部时钟周期的周期，同时使这些内部周期与测试周期同步，从而为每个内部循环提供相干数据。

公开(公告)号：US08611169B2

公开(公告)日：2013-12-17

申请号：US13315604

申请日：2011-12-09

申请人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

发明人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C8/08 ,  G11C8/10

摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.

摘要翻译： 描述了一种用于提供存储器阵列的精细粒度电源门控的方法。 在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。 激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线 存储器阵列中的剩余行被提供电源门控电压值。

公开(公告)号：US20120075919A1

公开(公告)日：2012-03-29

申请号：US12892191

申请日：2010-09-28

申请人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.

摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

公开(公告)号：US07894291B2

公开(公告)日：2011-02-22

申请号：US11162847

申请日：2005-09-26

申请人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

发明人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.

摘要翻译： 提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。 存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值 消费。 电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。 存储器的存储单元阵列可操作以存储数据。 在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。 这在待机模式期间允许数据保存在存储器中。 在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。 在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

公开(公告)号：US07548080B2

公开(公告)日：2009-06-16

申请号：US11538833

申请日：2006-10-05

申请人： Wagdi W. Abadeer ,  Harold Pilo ,  Daryl M. Seitzer

发明人： Wagdi W. Abadeer ,  Harold Pilo ,  Daryl M. Seitzer

IPC分类号： G01R31/02

CPC分类号： G01R31/287 ,  G01R31/2874

摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

摘要翻译： 本发明提供一种用于优化集成电路的老化的方法和装置。 该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

公开(公告)号：US20090080276A1

公开(公告)日：2009-03-26

申请号：US11859775

申请日：2007-09-23

申请人： Jin Cai ,  Randy William Mann ,  Harold Pilo

发明人： Jin Cai ,  Randy William Mann ,  Harold Pilo

IPC分类号： G05F1/567 ,  G11C7/04 ,  H03K17/16

CPC分类号： H03K19/0016 ,  H03K19/00369

摘要： A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals.

摘要翻译： 公开了一种产生这种偏置电压的电路，当偏置电压由半导体芯片的大量多个器件接收时，在待机模式下，在任何特定的工作温度下都会降低功耗。 所公开的电路包括至少一个监控FET，其保持在其截止状态，并且与大量多个FET器件具有共同的特性。 检测监控FET的温度依赖性漏电流，并用于产生与泄漏电流成正比的偏置电压。 该偏置电压由大型多个FET器件在其栅极电极或其主体端子上接收。

公开(公告)号：US07495950B2

公开(公告)日：2009-02-24

申请号：US11926689

申请日：2007-10-29

申请人： John A. Fifield ,  Harold Pilo

发明人： John A. Fifield ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.

摘要翻译： 包括多个SRAM单元，多个字线（WL0-WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器的静态随机存取存储器（SRAM）。 确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。 在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL） 对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

公开(公告)号：US20080219069A1

公开(公告)日：2008-09-11

申请号：US11684225

申请日：2007-03-09

申请人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

IPC分类号： G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/028

摘要： Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.

摘要翻译： 公开了用于减少和/或消除错配的方法的实施例。 这些实施例在芯片烧录之前对需要平衡状态的一个或多个电路子部件（例如，在每个存储器单元中的交叉耦合晶体管的偏置和/或存储器阵列中的读出放大器）进行采样， 通过启动老化过程，在该过程中，单独选择的状态被应用于电路中的每个设备。 这使得设备远离其优选的状态并且朝向平衡状态。 在老化过程中定期重新评估偏差，以避免过度校正。 通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。