公开(公告)号：US06272520B1

公开(公告)日：2001-08-07

申请号：US09001545

申请日：1997-12-31

申请人： Harshvardhan Sharangpani ,  Rajiv Gupta ,  Judge K. Arora

发明人： Harshvardhan Sharangpani ,  Rajiv Gupta ,  Judge K. Arora

IPC分类号： G06F900

CPC分类号： G06F9/3851 ,  G06F9/3824 ,  G06F9/3838

摘要： A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.

摘要翻译： 用于检测线程切换条件的方法为寄存器文件中的每个寄存器提供第一和第二记分板位。 当产生负载以将数据返回到寄存器时，与寄存器相关联的第一记分板位置1。 如果所选处理器高速缓存中的加载丢失，则第二个记分板位置1。 监视寄存器读取指令，当在其第一和第二记分板位被置位时检测到寄存器的寄存器读取指令时指示线程切换条件。

公开(公告)号：US06219781B1

公开(公告)日：2001-04-17

申请号：US09223240

申请日：1998-12-30

申请人： Judge K. Arora

发明人： Judge K. Arora

IPC分类号： G06F938

CPC分类号： G06F9/3838 ,  G06F9/30072 ,  G06F9/3842

摘要： Performing hazard detection in the presence of predication. The status of a consumer register associated with a consumer instruction is determined. The status and value of a predicate associated with the consumer instruction is also determined. A hazard signal is then sent based the status of the consumer register, the status of the predicate, and the value of the predicate.

摘要翻译： 在有预报的情况下进行危险检测。 确定与消费者指令相关联的消费者注册的状态。 还确定与消费者指令相关联的谓词的状态和值。 然后根据消费者注册的状态，谓词的状态和谓词的值发送危险信号。

公开(公告)号：US06442678B1

公开(公告)日：2002-08-27

申请号：US09224412

申请日：1998-12-31

申请人： Judge K. Arora

发明人： Judge K. Arora

IPC分类号： G06F938

CPC分类号： G06F9/3863 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842

摘要： In one method, a processor comprises both a speculative register file to store speculative register values and an architectural register file to store architectural register values. An output of the architectural register file is coupled to an input of the speculative register file to update the speculative register file when a misspeculation is detected.

摘要翻译： 在一种方法中，处理器包括用于存储推测寄存器值的推测寄存器文件和用于存储架构寄存器值的架构寄存器文件。 结构寄存器文件的输出耦合到推测寄存器文件的输入，以在检测到错误时更新推测寄存器文件。

公开(公告)号：US5860017A

公开(公告)日：1999-01-12

申请号：US672621

申请日：1996-06-28

申请人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

发明人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

摘要： A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately. Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces the performance penalty related to mispredictions.

公开(公告)号：US06199144B1

公开(公告)日：2001-03-06

申请号：US09001336

申请日：1997-12-31

申请人： Judge K. Arora ,  William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

发明人： Judge K. Arora ,  William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

IPC分类号： G06F1200

CPC分类号： G06F12/0833

摘要： A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.

摘要翻译： 一种用于将数据从计算机系统中的第一存储器位置传送到第二存储器位置的方法和装置。 执行加载指令，并且作为响应，在单个总线事务期间，数据从第一存储器位置传送到第二存储器位置。 在相同的总线事务期间，如果加载指令指示这样做，则请求使存储在第三存储器位置的数据的副本无效。

公开(公告)号：US6065115A

公开(公告)日：2000-05-16

申请号：US58460

申请日：1998-04-10

申请人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

发明人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

IPC分类号： G06F9/38 ,  G06F15/60

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

摘要： A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately. Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces the performance penalty related to mispredictions.

摘要翻译： 一种用于在程序流中有效处理指令的微处理器，包括诸如分支指令之类的条件程序流程控制指令。 条件程序流程控制指令如果条件被解析为满足则针对要处理的第一代码段，以及如果条件被解析为不满足则要处理的第二代码段。 提取单元获取要处理的指令，并且耦合到提取单元的分支预测逻辑预测条件的分辨率。 本发明的分支预测逻辑还确定不可能准确地预测条件的分辨率。 响应于分支预测逻辑的流管理逻辑在解决条件之前指导来自第一和第二代码部分的指令的推测性处理，如果条件的分辨率不太可能被准确地预测。 然后，正确执行的指令的结果将以程序顺序提交到架构状态。 以这种方式，本发明降低了与错误预测相关的性能损失。

公开(公告)号：US5948095A

公开(公告)日：1999-09-07

申请号：US1548

申请日：1997-12-31

申请人： Judge K. Arora ,  Jack D. Mills ,  Jerome C. Huck

发明人： Judge K. Arora ,  Jack D. Mills ,  Jerome C. Huck

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/383

摘要： A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

公开(公告)号：US5832260A

公开(公告)日：1998-11-03

申请号：US581031

申请日：1995-12-29

申请人： Judge K. Arora ,  Gary N. Hammond ,  Harshvardhan P. Sharangpani

发明人： Judge K. Arora ,  Gary N. Hammond ,  Harshvardhan P. Sharangpani

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/30058 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846

摘要： A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict. The execution unit of the invention executes the candidate instructions if the conditional program flow control instruction is resolved to be not taken and ignores the candidate instructions, through no-ops in one embodiment, if the conditional program flow control instruction is resolved to be taken, thus avoiding a misprediction penalty.

摘要翻译： 一种用于在包括程序流控制指令的程序中有效处理指令的处理器微体系结构。 程序流控制指令指定目标指令，并且包括目标指令和程序流控制指令之间的一个或多个候选指令。 提取单元从存储器中获取程序中的指令。 控制逻辑在解决条件程序流程控制指令之前，将缓冲器中的一个或多个候选指令存储在响应于取出单元从条件程序流控制指令获取指定预定数目的指令内的目标指令的程序流控制指令 。 在另一个实施例中，仅当条件分支指令被认为难以预测时才存储候选指令。 如果条件程序流程控制指令被解决为不被采用，则本发明的执行单元通过无操作在一个实施例中忽略候选指令，如果条件程序流控制指令被解决为采用，则执行候选指令， 从而避免误判。

公开(公告)号：US06629238B1

公开(公告)日：2003-09-30

申请号：US09474462

申请日：1999-12-29

申请人： Judge K. Arora ,  Tse-Yu Yeh

发明人： Judge K. Arora ,  Tse-Yu Yeh

IPC分类号： G06F938

CPC分类号： G06F9/3867 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/3842 ,  G06F9/3844

摘要： The present invention provides a mechanism for predicting whether a predicate is written and a value of the predicate to be written. For one embodiment, a predicate predictor is used to predict whether a predicate, in some cases a stage predicate, is written and a value to be written for the predicate, using the branch type and branch prediction information supplied by a branch predictor. The predicted stage predicate value controls data hazard handling and data bypasses operations for intermediate stages of the processor's instruction execution pipeline. The predicted stage predicate value may be validated when the modulo-scheduled loop instruction is resolved at the back end of the instruction execution pipeline.

摘要翻译： 本发明提供了一种用于预测谓词是否被写入的机制和要写入的谓词的值。 对于一个实施例，谓词预测器用于使用由分支预测器提供的分支类型和分支预测信息来预测谓词（在某些情况下是舞台谓词）是否被写入，并且为谓词写入的值。 预测阶段谓词值控制处理器指令执行管线的中间阶段的数据危险处理和数据旁路操作。 当在指令执行管线的后端解决模数调度循环指令时，可以验证预测阶段谓词值。

公开(公告)号：US06598156B1

公开(公告)日：2003-07-22

申请号：US09471308

申请日：1999-12-23

申请人： Judge K. Arora

发明人： Judge K. Arora

IPC分类号： G06F938

CPC分类号： G06F9/3861 ,  G06F9/3834 ,  G06F9/3853

摘要： A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.

摘要翻译： 提供了一种用于从执行高级加载指令的处理器中的故障负载检查指令中恢复的机制。 高级加载地址表（ALAT）跟踪高级加载指令的状态信息。 当处理相关联的负载检查操作时，状态信息被读取，并且如果状态信息指示由高级加载操作返回的数据被随后的存储操作修改则触发异常。 负载检查指令被转换为加载操作，指令从处理器的指令执行流水线中刷新，流水线被重新安装到负载检查指令之后的第一条指令。